From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 334FA3A7F7C for ; Tue, 24 Feb 2026 16:36:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771950993; cv=none; b=Wl5d2Gh/esLSfx6zox4o+riA6PJiMoWUkXm4uk+VcCwNGvAUVbk3pxJqDSRQqy1jcUHtT3DaoYwoRgdShefP9ztjNchMdkHy8l1l0J9tA/vA+9CA7R6ymcXIlH6nXKibW7D4wY2fVXMQ9Lc1El6Ej79wRW57hsUi8jnVFHPXci0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771950993; c=relaxed/simple; bh=+KRsXSo8ov1yzjRQREo4WOccpNE4GYaKU4CCBoVqcaU=; h=Date:Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type; b=sQY13e8ANOMGmSOofx5aiNVxMO1v5CP519g5bXIQXUJeya3V12WpVDqWL8/hiBSpNUM3jJ9jJYL335hPMnQnnhFztvr28bLyAULCy7PUOUo8PEAuMb9x2zfYDayyHjsMwIMw3ZZFBTEUA1nABkThHs5iHSm+uYX77a/m0MWQHUo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aKZuEOVr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aKZuEOVr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 82146C116D0; Tue, 24 Feb 2026 16:36:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771950993; bh=+KRsXSo8ov1yzjRQREo4WOccpNE4GYaKU4CCBoVqcaU=; h=Date:From:To:Cc:Subject:References:From; b=aKZuEOVr8/EDuzKTjR4ztOrkG83+M1i9hnBMZLOlxCmYHYyOIH1Rfvta2QXOkXb52 P3FdFQ69pvVG5S6s6ucp6Mg8J3LOOj3HXJ3v+va9TleXqVaSa+TdB/U+Jp7Dfo4i+D XhE6srILbr0/v2j7mNPrQIdl2lI58o+B6FfmVtdSNR8FOPHy20RNWt60TH4J5VUlxM w+Uer2YMrhAncp3fZVCycT3lgfameFpAJdcdvIg/pkxcfYgTjj84Il3fuXWr2CkVFK V0kIBCsar5fSSo+FIs+v3mB8jTcEXgW5Sf6BIGXBe7lko4w8vL8oeGxzdBvq+aBe1S PZXulfSqxshJg== Date: Tue, 24 Feb 2026 17:36:29 +0100 Message-ID: <20260224163429.809059527@kernel.org> User-Agent: quilt/0.68 From: Thomas Gleixner To: LKML Cc: Anna-Maria Behnsen , John Stultz , Stephen Boyd , Daniel Lezcano , Juri Lelli , Vincent Guittot , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , x86@kernel.org, Peter Zijlstra , Frederic Weisbecker , Eric Dumazet Subject: [patch 16/48] x86/apic: Remove pointless fence in lapic_next_deadline() References: <20260224163022.795809588@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 lapic_next_deadline() contains a fence before the TSC read and the write to the TSC_DEADLINE MSR with a content free and therefore useless comment: /* This MSR is special and need a special fence: */ The MSR is not really special. It is just not a serializing MSR, but that does not matter at all in this context as all of these operations are strictly CPU local. The only thing the fence prevents is that the RDTSC is speculated ahead, but that's not really relevant as the delta is calculated way before based on a previous TSC read and therefore inaccurate by definition. So removing the fence is just making it slightly more inaccurate in the worst case, but that is irrelevant as it's way below the actual system immanent latencies and variations. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/apic/apic.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -412,22 +412,20 @@ EXPORT_SYMBOL_GPL(setup_APIC_eilvt); /* * Program the next event, relative to now */ -static int lapic_next_event(unsigned long delta, - struct clock_event_device *evt) +static int lapic_next_event(unsigned long delta, struct clock_event_device *evt) { apic_write(APIC_TMICT, delta); return 0; } -static int lapic_next_deadline(unsigned long delta, - struct clock_event_device *evt) +static int lapic_next_deadline(unsigned long delta, struct clock_event_device *evt) { - u64 tsc; + /* + * There is no weak_wrmsr_fence() required here as all of this is purely + * CPU local. Avoid the [ml]fence overhead. + */ + u64 tsc = rdtsc(); - /* This MSR is special and need a special fence: */ - weak_wrmsr_fence(); - - tsc = rdtsc(); wrmsrq(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); return 0; }