From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AF863A7F77 for ; Tue, 24 Feb 2026 16:36:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771950998; cv=none; b=laQ0HsWnkKUAE+MscabA6gkwP/c0Zkwmdr6fyFcX68ThYXeouVHAPZsD568gFmklikR8JVlY1coKuOuD6NLI9JS34AIN/VAK36haWN8BpQJ+7X3bnXkxZYYf3F5DxDaz/tyXUmBZxTfn54/EE84PC3KvzZflKDSk46l2W36/V8E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771950998; c=relaxed/simple; bh=KMAUtK4LlktSqiMOuizW9zq5JIPy3BF7H8cr4poWS2s=; h=Date:Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type; b=Ij8YXniE7Tg8x755X5vbK/BS3E3fwCulgvCoCqpYv2SlaMQKJkhsgQOPt3Nsx2yv/xAnmhMf6duBAFNH7Lq07jSmWfM0UTdDrIXJ78f5HOFe06RXlOFj+guJqZhCODUr6UcRZkuFhJroHTOk+M2FRYWO8aJCWqx+01+EnbF/dxA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KO9tfLgf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KO9tfLgf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6FE49C19422; Tue, 24 Feb 2026 16:36:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771950998; bh=KMAUtK4LlktSqiMOuizW9zq5JIPy3BF7H8cr4poWS2s=; h=Date:From:To:Cc:Subject:References:From; b=KO9tfLgfIRi7e7gwNb4Dmhp9jS5tI61LpOumrgZYa+8PqKHX51FI8tMJV/4a+vRry oXg7sRLKblyYsmWS8tA2RyMtrxcHrYsGZLB1MRevbRRoTISQbDoqEtuirmpUmIHolJ BNxSaz2gJk2xzRejM0klHDbxNrNFhBfQs3YLgniPOoESaMmJRmO/SKSfnhTUUuZcyD g7aYJV3KZq1GVekpq2PDJNnIDUUK1TmO6vzmlAdXecghz8DlQMH1HDB0DKrtVfuHGQ x5SqGbdVhdWrPEJDm1rStwwF1vovkPQ4Uv10rbZPvT99M85cneHYaQH9EuZYmKi7uV +VrSH6KR9VyPw== Date: Tue, 24 Feb 2026 17:36:34 +0100 Message-ID: <20260224163429.877429827@kernel.org> User-Agent: quilt/0.68 From: Thomas Gleixner To: LKML Cc: Anna-Maria Behnsen , John Stultz , Stephen Boyd , Daniel Lezcano , Juri Lelli , Vincent Guittot , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , x86@kernel.org, Peter Zijlstra , Frederic Weisbecker , Eric Dumazet Subject: [patch 17/48] x86/apic: Avoid the PVOPS indirection for the TSC deadline timer References: <20260224163022.795809588@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 XEN PV does not emulate the TSC deadline timer, so the PVOPS indirection for writing the deadline MSR can be avoided completely. Use native_wrmsrq() instead. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/apic/apic.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -426,7 +426,7 @@ static int lapic_next_deadline(unsigned */ u64 tsc = rdtsc(); - wrmsrq(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); + native_wrmsrq(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); return 0; } @@ -450,7 +450,7 @@ static int lapic_timer_shutdown(struct c * the timer _and_ zero the counter registers: */ if (v & APIC_LVT_TIMER_TSCDEADLINE) - wrmsrq(MSR_IA32_TSC_DEADLINE, 0); + native_wrmsrq(MSR_IA32_TSC_DEADLINE, 0); else apic_write(APIC_TMICT, 0); @@ -547,6 +547,11 @@ static __init bool apic_validate_deadlin if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) return false; + + /* XEN_PV does not support it, but be paranoia about it */ + if (boot_cpu_has(X86_FEATURE_XENPV)) + goto clear; + if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) return true; @@ -559,9 +564,11 @@ static __init bool apic_validate_deadlin if (boot_cpu_data.microcode >= rev) return true; - setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " "please update microcode to version: 0x%x (or later)\n", rev); + +clear: + setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); return false; }