From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 127D9392C42 for ; Mon, 2 Mar 2026 09:59:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772445545; cv=none; b=t6GbqXFoUSmqaauzS2lXeb4D3FFhmarVBKOCTIo2FVE03YAinZ/v+UoUyKHBaGfD1F0WI16IcAFqUPz5v+Iwhy0BFneQvFX86b883gE/fI3nBYG3TWTL/gsfkLxFVBC7Ree1RpBDdmyrF9+WuKc4DuDgwybfkopT9WR7sCPuwdY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772445545; c=relaxed/simple; bh=+U/a3l9efdYmCTx9oJhBq4AgxHYZOLO9mX+G/kxf3oc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gXCUfrm4kj6v5b5SdSH6w1StlpJ2rPvtaZQCFCrxLTZN5w33Ng5QxyPM6I5LWUcBPmzytjlzW5lStx4S0Umf0zrnsOd/PuoD+RXyaxYAFfX1NScNUfhq4xVajNetZIQsbGjh/751pCoT+m1SMihSIthWSUvqUoK1JRTqm7RW3kU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lRfLeDGo; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lRfLeDGo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772445544; x=1803981544; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+U/a3l9efdYmCTx9oJhBq4AgxHYZOLO9mX+G/kxf3oc=; b=lRfLeDGoj3MW0J9ARdALVhPFndP1ND6cjImmw8sqQG/6xiBHUoYnIn9P cJS6y25JuKr5MhMVEcrsi3B6zYPWRtj4VTp2jDIcnRoiMm//cY5/KwQgR peutWoC/kEsP7X02W02Kp/Bzk6avsriXZvqQMcAPC0iE9ZKXPnDYmr2mu WGvHNNtONcX2ner/xxSIVs7FkC8YSd8siZK05w26AD+KpIz/HNK5adC2i N83G6sDrL/3mqybiwa53TFXwZZKzJY7OuEiEjWKz8e29OrP07BBPzz0cg Hhr447+k3CkLKk8hrRSCM8bEnJ7BZDz6EW4uUB0SdlkyfBlgpP/IQEGq9 Q==; X-CSE-ConnectionGUID: c2SNTeCJTrWq5LJO8b/z0A== X-CSE-MsgGUID: 7uXfIVrUQ8W2Yo67Rp5INw== X-IronPort-AV: E=McAfee;i="6800,10657,11716"; a="96066027" X-IronPort-AV: E=Sophos;i="6.21,319,1763452800"; d="scan'208";a="96066027" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2026 01:58:52 -0800 X-CSE-ConnectionGUID: z4WytTbeSEestykCDzTCqg== X-CSE-MsgGUID: GEizdR+lRxaHwEmvS26MIw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,319,1763452800"; d="scan'208";a="217628235" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa008.jf.intel.com with ESMTP; 02 Mar 2026 01:58:51 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id F195A98; Mon, 02 Mar 2026 10:58:49 +0100 (CET) From: Andy Shevchenko To: Mark Brown , Andy Shevchenko , linux-kernel@vger.kernel.org, driver-core@lists.linux.dev Cc: Greg Kroah-Hartman , "Rafael J. Wysocki" , Danilo Krummrich Subject: [PATCH v4 1/3] regcache: Move HW readback after cache initialisation Date: Mon, 2 Mar 2026 10:56:55 +0100 Message-ID: <20260302095847.2310066-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260302095847.2310066-1-andriy.shevchenko@linux.intel.com> References: <20260302095847.2310066-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Make sure that cache is initialised before calling any IO using regmap, this makes sure that we won't access NULL or invalid pointers in the cache which hasn't been initialised. Signed-off-by: Andy Shevchenko --- drivers/base/regmap/regcache.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c index 73cfe8120669..ae60411ea8dc 100644 --- a/drivers/base/regmap/regcache.c +++ b/drivers/base/regmap/regcache.c @@ -67,6 +67,14 @@ static int regcache_hw_init(struct regmap *map, int count) unsigned int reg, val; void *tmp_buf; + /* + * When count is zero, it means there is nothing to cache and hence + * nothing to read back from HW to set up defaults, so skip this phase + * without an error code returned. + */ + if (!count) + return 0; + map->num_reg_defaults = count; map->reg_defaults = kmalloc_objs(struct reg_default, count); if (!map->reg_defaults) @@ -202,14 +210,6 @@ int regcache_init(struct regmap *map, const struct regmap_config *config) count = regcache_count_cacheable_registers(map); if (map->cache_bypass) return 0; - - /* Some devices such as PMICs don't have cache defaults, - * we cope with this by reading back the HW registers and - * crafting the cache defaults by hand. - */ - ret = regcache_hw_init(map, count); - if (ret < 0) - return ret; } if (!map->max_register_is_set && map->num_reg_defaults_raw) { @@ -227,6 +227,15 @@ int regcache_init(struct regmap *map, const struct regmap_config *config) goto err_free; } + /* + * Some devices such as PMICs don't have cache defaults, + * we cope with this by reading back the HW registers and + * crafting the cache defaults by hand. + */ + ret = regcache_hw_init(map, count); + if (ret) + goto err_exit; + if (map->cache_ops->populate && (map->num_reg_defaults || map->reg_default_cb)) { dev_dbg(map->dev, "Populating %s cache\n", map->cache_ops->name); -- 2.50.1