Re: [PATCH 2/2] watchdog: at91sam9_wdt.h: Document WDDIS bit position per SoC family

Alexandre Belloni
2026-03-02T14:32:35Z

On 02/03/2026 17:03:10+0530, Balakrishnan Sambath wrote:
> AT91_WDT_WDDIS (bit 15) applies to SAMA5/AT91SAM9261 and
> AT91_SAM9X60_WDDIS (bit 12) to SAM9X60/SAMA7G5/SAM9X75. Update
> comments to reflect this and add SAMA7G5 and SAM9X75 datasheet
> references to the file header.
>
> Signed-off-by: Balakrishnan Sambath <balakrishnan.s@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>

> ---
> drivers/watchdog/at91sam9_wdt.h | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/watchdog/at91sam9_wdt.h b/drivers/watchdog/at91sam9_wdt.h
> index 298d545df1a1..2020694f8f6f 100644
> --- a/drivers/watchdog/at91sam9_wdt.h
> +++ b/drivers/watchdog/at91sam9_wdt.h
> @@ -3,40 +3,42 @@
> * drivers/watchdog/at91sam9_wdt.h
> *
> * Copyright (C) 2007 Andrew Victor
> * Copyright (C) 2007 Atmel Corporation.
> * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
> *
> * Watchdog Timer (WDT) - System peripherals regsters.
> * Based on AT91SAM9261 datasheet revision D.
> * Based on SAM9X60 datasheet.
> + * Based on SAMA7G5 datasheet.
> + * Based on SAM9X75 datasheet.
> *
> */
>
> #ifndef AT91_WDT_H
> #define AT91_WDT_H
>
> #include <linux/bits.h>
>
> #define AT91_WDT_CR 0x00 /* Watchdog Control Register */
> #define AT91_WDT_WDRSTT BIT(0) /* Restart */
> #define AT91_WDT_KEY (0xa5UL << 24) /* KEY Password */
>
> #define AT91_WDT_MR 0x04 /* Watchdog Mode Register */
> #define AT91_WDT_WDV (0xfffUL << 0) /* Counter Value */
> #define AT91_WDT_SET_WDV(x) ((x) & AT91_WDT_WDV)
> #define AT91_SAM9X60_PERIODRST BIT(4) /* Period Reset */
> #define AT91_SAM9X60_RPTHRST BIT(5) /* Minimum Restart Period */
> #define AT91_WDT_WDFIEN BIT(12) /* Fault Interrupt Enable */
> -#define AT91_SAM9X60_WDDIS BIT(12) /* Watchdog Disable */
> +#define AT91_SAM9X60_WDDIS BIT(12) /* Watchdog Disable (SAM9X60, SAMA7G5, SAM9X75) */
> #define AT91_WDT_WDRSTEN BIT(13) /* Reset Processor */
> #define AT91_WDT_WDRPROC BIT(14) /* Timer Restart */
> -#define AT91_WDT_WDDIS BIT(15) /* Watchdog Disable */
> +#define AT91_WDT_WDDIS BIT(15) /* Watchdog Disable (SAMA5, AT91SAM9261) */
> #define AT91_WDT_WDD (0xfffUL << 16) /* Delta Value */
> #define AT91_WDT_SET_WDD(x) (((x) << 16) & AT91_WDT_WDD)
> #define AT91_WDT_WDDBGHLT BIT(28) /* Debug Halt */
> #define AT91_WDT_WDIDLEHLT BIT(29) /* Idle Halt */
>
> #define AT91_WDT_SR 0x08 /* Watchdog Status Register */
> #define AT91_WDT_WDUNF BIT(0) /* Watchdog Underflow */
> #define AT91_WDT_WDERR BIT(1) /* Watchdog Error */
>
> --
> 2.34.1
>

--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering