From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5DC52AD03 for ; Mon, 2 Mar 2026 16:33:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772469191; cv=none; b=JWPDuAeqxZcpJGEIFqDrNXxZ26b43bhn8SotEx8A5UddoR/+/azGD9La13ZzJWiPWm/IDM6aXlh3dldTdTNhdhJALr3yw6RcwJfWHqUe9UV8Iq+WRzEGHaaJ2zBF6RBd+hn06qQQrqT5rsMV6h8/kM2OY+GQBitsUt20o8+JBqE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772469191; c=relaxed/simple; bh=kfMIc0OUpsgkTCkMzSFFXGItn5Z0YPAU5KqBEO/YCjU=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version:Content-Type; b=ZfKA/Md3R2nNhjIh8Cw1W8PNBuoHQAuAz3qgo0dgZWfPesCAF6q3zW37cV0GsCUOqu8MAOtLwW5frQZKuGGfSYOdVW6iEaJLlXskM9ZUNXgCRmUc1W5x8D9jd5JMW6tX+OhtB0yaUFG/tGMEetvioupjh6qjDOvavT7XBoLkI+Y= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EDoYeeoS; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EDoYeeoS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772469189; x=1804005189; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=kfMIc0OUpsgkTCkMzSFFXGItn5Z0YPAU5KqBEO/YCjU=; b=EDoYeeoSXzVNeg58F2tWdkmC25codOYjcKqaeH0avXOfhC//0p+++uwl HojFDX4UR1M+Q99Bp0jwssWb7CKYxyoFeWjMixuEDyEEyYLZz1mzx+wcO EaJjkKQVILsan5+ggUjFlrGxIGnWb9+dl6//hsolvRd5MoRkPWh5qMI1L 1jz1k2m9D/GETRS3NZeqLS42aw7Ph1Xo4g2U8OFsTYH/VxPitQ6k6gXHe YQdmM/64cKusx60hrL/bKmgSYrIp9VzXZaJaa0NvKGQnZ4rPKxvCgoV2D hWj1m7cB/Xo6Fi+JCvICsj3TaVFhm+0GxZVQ3fBdLZuePiO3cwslPpWxE A==; X-CSE-ConnectionGUID: m9Sdm1i4QUWQCOqT9JnDwQ== X-CSE-MsgGUID: +ZL3OPXBSEKQttRI89PqEA== X-IronPort-AV: E=McAfee;i="6800,10657,11717"; a="73447807" X-IronPort-AV: E=Sophos;i="6.21,320,1763452800"; d="scan'208";a="73447807" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2026 08:33:09 -0800 X-CSE-ConnectionGUID: vr/4G302QFOqlxJOv5pghQ== X-CSE-MsgGUID: zDQUWEPnTW23jzI2q1uvMQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,320,1763452800"; d="scan'208";a="255564508" Received: from smoticic-mobl1.ger.corp.intel.com (HELO fedora) ([10.245.244.81]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2026 08:33:07 -0800 From: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= To: intel-xe@lists.freedesktop.org Cc: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Matthew Brost , Jason Gunthorpe , Andrew Morton , Simona Vetter , Dave Airlie , Alistair Popple , dri-devel@lists.freedesktop.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Christian=20K=C3=B6nig?= Subject: [PATCH v2 0/4] Two-pass MMU interval notifiers Date: Mon, 2 Mar 2026 17:32:44 +0100 Message-ID: <20260302163248.105454-1-thomas.hellstrom@linux.intel.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit GPU use-cases for mmu_interval_notifiers with hmm often involve starting a gpu operation and then waiting for it to complete. These operations are typically context preemption or TLB flushing. With single-pass notifiers per GPU this doesn't scale in multi-gpu scenarios. In those scenarios we'd want to first start preemption- or TLB flushing on all GPUs and as a second pass wait for them to complete. This also applies in non-recoverable page-fault scenarios to starting a preemption requests on GPUs and waiting for the GPUs to preempt so that system pages they access can be reclaimed. One can do this on per-driver basis multiplexing per-driver notifiers but that would mean sharing the notifier "user" lock across all GPUs and that doesn't scale well either, so adding support for two-pass in the core appears like the right choice. So this series does that, with pach 1 implementing the core support and also describes the choices made. The rest of the patches implements a POC with xeKMD userptr invalidation and potential TLB-flushing. A follow-up series will extend to drm_gpusvm. v2 hightlights: - Refactor the core mm patch to use the struct mmu_interval_notifier_ops for the invalidate_finish() callback. - Rebase on xe driver tlb invalidation changes. - Provide an initial implementation for userptr instead of drm_gpusvm. The intent is to handle drm_gpusvm in a follow-up series. Cc: Matthew Brost Cc: Jason Gunthorpe Cc: Andrew Morton Cc: Simona Vetter Cc: Dave Airlie Cc: Alistair Popple Cc: Cc: Cc: Thomas Hellström (4): mm/mmu_notifier: Allow two-pass struct mmu_interval_notifiers drm/xe/userptr: Convert invalidation to two-pass MMU notifier drm/xe: Split TLB invalidation into submit and wait steps drm/xe/userptr: Defer Waiting for TLB invalidation to the second pass if possible drivers/gpu/drm/xe/xe_svm.c | 6 +- drivers/gpu/drm/xe/xe_tlb_inval.c | 82 ++++++++++++++ drivers/gpu/drm/xe/xe_tlb_inval.h | 6 ++ drivers/gpu/drm/xe/xe_tlb_inval_types.h | 14 +++ drivers/gpu/drm/xe/xe_userptr.c | 136 ++++++++++++++++++++---- drivers/gpu/drm/xe/xe_userptr.h | 32 ++++++ drivers/gpu/drm/xe/xe_vm.c | 99 ++++++----------- drivers/gpu/drm/xe/xe_vm.h | 5 +- drivers/gpu/drm/xe/xe_vm_madvise.c | 9 +- drivers/gpu/drm/xe/xe_vm_types.h | 1 + include/linux/mmu_notifier.h | 38 +++++++ mm/mmu_notifier.c | 64 +++++++++-- 12 files changed, 389 insertions(+), 103 deletions(-) -- 2.53.0