[PATCH v2] ARM: dts: renesas: r9a06g032: Add support for CPU frequency scaling

[PATCH v2] ARM: dts: renesas: r9a06g032: Add support for CPU frequency scaling

[Herve Codina (Schneider Electric)]

In RZ/N1 SoCs, CPUs are allowed to work at 125, 250 or 500 MHz when the
'ref' clock frequency value is set to 500 MHz which is the default 'ref'
clock frequency value.

Add support for CPU frequency scaling defining those 3 frequencies in
the opp-table with the assumption that the 'ref' clock is set to its
default value.

Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
---
Changes v1 -> v2
  v1: https://lore.kernel.org/all/20260115160144.1200270-1-herve.codina@bootlin.com/

  Fix Author and SoB.

 arch/arm/boot/dts/renesas/r9a06g032.dtsi | 35 ++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
index 8debb77803bb..9f21d8fba940 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
@@ -15,6 +15,39 @@ / {
 	#size-cells = <1>;
 	interrupt-parent = <&gic>;
 
+	/*
+	 * The CPUs clock is based on the 'ref' clock (output of OPPDIV divisor)
+	 * with x1, x2 or x4 ratio between the CPUs clock frequency and this
+	 * 'ref' clock frequency.
+	 *
+	 * The table below is built on the assumption that the 'ref' clock
+	 * frequency is set to 500MHz which is its default value.
+	 *
+	 * The table should be overridden in the board device-tree file based
+	 * on the 'ref' clock frequency if this frequency value is not the
+	 * default one.
+	 */
+	cpu_opp_table: opp-table-cpu {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-125000000 {
+			opp-hz = /bits/ 64 <125000000>;
+			/* ~35 clocks cycles at 125mhz */
+			clock-latency-ns = <300>;
+		};
+
+		opp-250000000 {
+			opp-hz = /bits/ 64 <250000000>;
+			clock-latency-ns = <300>;
+		};
+
+		opp-500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			clock-latency-ns = <300>;
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -24,6 +57,7 @@ cpu@0 {
 			compatible = "arm,cortex-a7";
 			reg = <0>;
 			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
+			operating-points-v2 = <&cpu_opp_table>;
 		};
 
 		cpu@1 {
@@ -33,6 +67,7 @@ cpu@1 {
 			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
 			enable-method = "renesas,r9a06g032-smp";
 			cpu-release-addr = <0 0x4000c204>;
+			operating-points-v2 = <&cpu_opp_table>;
 		};
 	};
 
-- 
2.52.0

Re: [PATCH v2] ARM: dts: renesas: r9a06g032: Add support for CPU frequency scaling

[Geert Uytterhoeven]

Hi Hervé,

On Thu, 15 Jan 2026 at 17:49, Herve Codina (Schneider Electric)
<herve.codina@bootlin.com> wrote:
> In RZ/N1 SoCs, CPUs are allowed to work at 125, 250 or 500 MHz when the
> 'ref' clock frequency value is set to 500 MHz which is the default 'ref'
> clock frequency value.
>
> Add support for CPU frequency scaling defining those 3 frequencies in
> the opp-table with the assumption that the 'ref' clock is set to its
> default value.
>
> Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>

Thanks for your patch, which LGTM.

> --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi

> @@ -24,6 +57,7 @@ cpu@0 {
>                         compatible = "arm,cortex-a7";
>                         reg = <0>;
>                         clocks = <&sysctrl R9A06G032_CLK_A7MP>;
> +                       operating-points-v2 = <&cpu_opp_table>;
>                 };
>
>                 cpu@1 {

Unless I am missing something, the RZ/N1 clock driver does not support
the A7MP clock yet, so how can cpufreq work for you?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2] ARM: dts: renesas: r9a06g032: Add support for CPU frequency scaling

[Herve Codina]

On Mon, 2 Mar 2026 18:04:36 +0100
Geert Uytterhoeven <geert@linux-m68k.org> wrote:

> Hi Hervé,
> 
> On Thu, 15 Jan 2026 at 17:49, Herve Codina (Schneider Electric)
> <herve.codina@bootlin.com> wrote:
> > In RZ/N1 SoCs, CPUs are allowed to work at 125, 250 or 500 MHz when the
> > 'ref' clock frequency value is set to 500 MHz which is the default 'ref'
> > clock frequency value.
> >
> > Add support for CPU frequency scaling defining those 3 frequencies in
> > the opp-table with the assumption that the 'ref' clock is set to its
> > default value.
> >
> > Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>  
> 
> Thanks for your patch, which LGTM.
> 
> > --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
> > +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi  
> 
> > @@ -24,6 +57,7 @@ cpu@0 {
> >                         compatible = "arm,cortex-a7";
> >                         reg = <0>;
> >                         clocks = <&sysctrl R9A06G032_CLK_A7MP>;
> > +                       operating-points-v2 = <&cpu_opp_table>;
> >                 };
> >
> >                 cpu@1 {  
> 
> Unless I am missing something, the RZ/N1 clock driver does not support
> the A7MP clock yet, so how can cpufreq work for you?

R9A06G032_CLK_A7MP is DIV_CA7

https://elixir.bootlin.com/linux/v6.19.3/source/include/dt-bindings/clock/r9a06g032-sysctrl.h#L78
https://elixir.bootlin.com/linux/v6.19.3/source/drivers/clk/renesas/r9a06g032-clocks.c#L261
https://elixir.bootlin.com/linux/v6.19.3/source/drivers/clk/renesas/r9a06g032-clocks.c#L455

And on my system, got the following:
  # cat /sys/devices/system/cpu/cpufreq/policy0/stats/time_in_state 
  125000 4574
  250000 108
  500000 392
  #

All defined opp-hz values seems to be used without any errors. I hope that
any errors would be reported in kernel logs. At least this one:
  https://elixir.bootlin.com/linux/v6.19.3/source/drivers/cpufreq/cpufreq.c#L2329


Best regards,
Hervé

Re: [PATCH v2] ARM: dts: renesas: r9a06g032: Add support for CPU frequency scaling

[Geert Uytterhoeven]

Hi Hervé,

On Mon, 2 Mar 2026 at 18:23, Herve Codina <herve.codina@bootlin.com> wrote:
> On Mon, 2 Mar 2026 18:04:36 +0100
> Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> > Hi Hervé,
> >
> > On Thu, 15 Jan 2026 at 17:49, Herve Codina (Schneider Electric)
> > <herve.codina@bootlin.com> wrote:
> > > In RZ/N1 SoCs, CPUs are allowed to work at 125, 250 or 500 MHz when the
> > > 'ref' clock frequency value is set to 500 MHz which is the default 'ref'
> > > clock frequency value.
> > >
> > > Add support for CPU frequency scaling defining those 3 frequencies in
> > > the opp-table with the assumption that the 'ref' clock is set to its
> > > default value.
> > >
> > > Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
> >
> > Thanks for your patch, which LGTM.
> >
> > > --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
> > > +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
> >
> > > @@ -24,6 +57,7 @@ cpu@0 {
> > >                         compatible = "arm,cortex-a7";
> > >                         reg = <0>;
> > >                         clocks = <&sysctrl R9A06G032_CLK_A7MP>;
> > > +                       operating-points-v2 = <&cpu_opp_table>;
> > >                 };
> > >
> > >                 cpu@1 {
> >
> > Unless I am missing something, the RZ/N1 clock driver does not support
> > the A7MP clock yet, so how can cpufreq work for you?
>
> R9A06G032_CLK_A7MP is DIV_CA7

Thank you!

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.1.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds