From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1FDA4266A4; Mon, 2 Mar 2026 17:23:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772472228; cv=none; b=UYbIXv5VE+dFVoFZ2zMNJDAO2No+iLSentqMwcFMefggtQTARPGJYOwTG8pjTVOzBOnWNNF3isGGM8riSxVK9XsZ+FJFl/4JKZneipJ33RlG+EDgy6XGat6RMPIEpPZegaap6d1X0ohn7xfblvaGC6vm8aXg+OJwKU6/J/ny99I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772472228; c=relaxed/simple; bh=lsqoijld0gAdVfIcfMKRJZDiGviXR1wEv1HLS/9y7b4=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lU5zPugqF6QaF7qshoQBP6PIfg3yjXLOjgZwyn54AZOToNMOC5RHgGWF0xzqwoSDlT9WBKWc2KlayU9etSn+WREbCcYFwX35NIBJbLKohtV3GMvEbjaJDdzlhHDt/Air+0PWz4w4WwOzwmkTxfc6bgXKIB31wRP0FlAogj6Z9/w= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=2bZcrrQ3; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="2bZcrrQ3" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 587734E41126; Mon, 2 Mar 2026 17:23:43 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 1337C5FE89; Mon, 2 Mar 2026 17:23:43 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 8545E103686D8; Mon, 2 Mar 2026 18:23:37 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772472222; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=/aeeLY5nCjJLoCOrscAC1ow5AwnqUo867Edx/KaGydM=; b=2bZcrrQ3nyqiGFzPmuml2QFGFv2Sj5GXVH1NYS5Rynl5ah9/35dlksWhR3LH0JN1aF+/au a+O/tG6gT0Gtmicxzm7yFzr9AUwIogZbbRL2SKZnNR1SzANYZ9d5euwhA1ZubW8tQitqHM +Rpt0kZK6/9X6dwQO9hNSre3IuK2txxlhn29e1RyO+CFqa4b3sMzxoAPNA2pvvUul6N5Yr hXdELycHMylOxKSg7bbycYQqaWTm07blL4orH6rVqacCBrqc/M8dwUe/wrDghN3PGLC4W7 UOCjFtYAk2jjKUSRR8fSL2CyC1MCTc2kQY1ldsR4E7SqN/zK4H/yrY8+x3Vcwg== Date: Mon, 2 Mar 2026 18:23:35 +0100 From: Herve Codina To: Geert Uytterhoeven Cc: Wolfram Sang , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pascal Eberhard , Miquel Raynal , Thomas Petazzoni Subject: Re: [PATCH v2] ARM: dts: renesas: r9a06g032: Add support for CPU frequency scaling Message-ID: <20260302182335.312e0c3a@bootlin.com> In-Reply-To: References: <20260115164905.1203453-1-herve.codina@bootlin.com> Organization: Bootlin X-Mailer: Claws Mail 4.3.1 (GTK 3.24.49; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 On Mon, 2 Mar 2026 18:04:36 +0100 Geert Uytterhoeven wrote: > Hi Hervé, > > On Thu, 15 Jan 2026 at 17:49, Herve Codina (Schneider Electric) > wrote: > > In RZ/N1 SoCs, CPUs are allowed to work at 125, 250 or 500 MHz when the > > 'ref' clock frequency value is set to 500 MHz which is the default 'ref' > > clock frequency value. > > > > Add support for CPU frequency scaling defining those 3 frequencies in > > the opp-table with the assumption that the 'ref' clock is set to its > > default value. > > > > Signed-off-by: Herve Codina (Schneider Electric) > > Thanks for your patch, which LGTM. > > > --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi > > +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi > > > @@ -24,6 +57,7 @@ cpu@0 { > > compatible = "arm,cortex-a7"; > > reg = <0>; > > clocks = <&sysctrl R9A06G032_CLK_A7MP>; > > + operating-points-v2 = <&cpu_opp_table>; > > }; > > > > cpu@1 { > > Unless I am missing something, the RZ/N1 clock driver does not support > the A7MP clock yet, so how can cpufreq work for you? R9A06G032_CLK_A7MP is DIV_CA7 https://elixir.bootlin.com/linux/v6.19.3/source/include/dt-bindings/clock/r9a06g032-sysctrl.h#L78 https://elixir.bootlin.com/linux/v6.19.3/source/drivers/clk/renesas/r9a06g032-clocks.c#L261 https://elixir.bootlin.com/linux/v6.19.3/source/drivers/clk/renesas/r9a06g032-clocks.c#L455 And on my system, got the following: # cat /sys/devices/system/cpu/cpufreq/policy0/stats/time_in_state 125000 4574 250000 108 500000 392 # All defined opp-hz values seems to be used without any errors. I hope that any errors would be reported in kernel logs. At least this one: https://elixir.bootlin.com/linux/v6.19.3/source/drivers/cpufreq/cpufreq.c#L2329 Best regards, Hervé