[PATCH v1 1/2] dt-bindings: mmc: snps,dwcmshc-sdhci: add HPE GSC dwcmshc compatible

[nick.hawkins@hpe.com]

From: Nick Hawkins <nick.hawkins@hpe.com>

Add the 'hpe,gsc-dwcmshc' compatible string for the HPE GSC (ARM64
Cortex-A53) BMC SoC eMMC controller.

The HPE GSC wires an additional 32-bit register, MSHCCS (eMMC
Configuration/Status Register).  This register
controls SCG sync disable (bit 18) for HS200 RX delay-line phase
selection and reflects the current data transfer width (bits 17:16).
A second reg entry is mandatory for this compatible to map MSHCCS.

The HPE GSC eMMC interface only exposes a single 'core' clock (no
bus clock), so clocks/clock-names are constrained to maxItems: 1.

Add an example node showing the two-entry reg layout (SDHCI base at
0xc0100000 and MSHCCS at 0xc0000110).

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
---
 .../bindings/mmc/snps,dwcmshc-sdhci.yaml      | 43 ++++++++++++++++++-
 1 file changed, 42 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
index 7e7c55dc2440..9c326dff589f 100644
--- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
@@ -23,6 +23,7 @@ properties:
           - const: sophgo,sg2044-dwcmshc
           - const: sophgo,sg2042-dwcmshc
       - enum:
+          - hpe,gsc-dwcmshc
           - rockchip,rk3568-dwcmshc
           - rockchip,rk3588-dwcmshc
           - snps,dwcmshc-sdhci
@@ -33,7 +34,8 @@ properties:
           - eswin,eic7700-dwcmshc
 
   reg:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
 
   interrupts:
     maxItems: 1
@@ -87,6 +89,35 @@ required:
 allOf:
   - $ref: mmc-controller.yaml#
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: hpe,gsc-dwcmshc
+
+    then:
+      properties:
+        reg:
+          items:
+            - description: SDHCI base registers
+            - description: |
+                MSHCCS register. A 32-bit register that controls SCG sync
+                disable (bit 18) for HS200 RX delay-line phase selection
+                and reflects the current data transfer width (bits 17:16).
+        clocks:
+          maxItems: 1
+          items:
+            - description: core clock
+        clock-names:
+          maxItems: 1
+          items:
+            - const: core
+
+    else:
+      properties:
+        reg:
+          maxItems: 1
+
   - if:
       properties:
         compatible:
@@ -190,5 +221,15 @@ examples:
       #address-cells = <1>;
       #size-cells = <0>;
     };
+  - |
+    mmc@c0100000 {
+      compatible = "hpe,gsc-dwcmshc";
+      reg = <0xc0100000 0x1000>, <0xc0000110 0x4>;
+      interrupts = <0 17 0x4>;
+      clocks = <&emmcclk>;
+      clock-names = "core";
+      bus-width = <8>;
+      non-removable;
+    };
 
 ...
-- 
2.34.1