From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B44E3EFD1A for ; Tue, 3 Mar 2026 21:30:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772573434; cv=none; b=WaeZi3PP1fWDRZ0Lu0/iPtDI6weHPBo7jy8QlreG07AG6bzhLLE4U1KJnO6bD1eFtsdiG2vFcR/JY1aZElfjhM94u3bZw+wY6Nyyz1DMC/SACZxSVvTcU5oyCKt6jusOAse4tAER7U+5mwzKtlWEGJNEECt8k7bEJx2BmAk2FRw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772573434; c=relaxed/simple; bh=LHKfw1JsvUuXSzGaff7KKEjSDwosIwKtpx+tw1jAbBg=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=OqWgW2/qaUfHEvFp4GEbJQXQU8ZHGRVXNPYzbTmvowobH0oDJRPWOVjKPi8ybpRzY6AYouc47IwCaSpxRyGafwzHOtWMwBMI7OuPhf7nB0U5gaUG+VFPm2CmpNMlt3+Zcq3xIGysTLposWTTPq1SH5195X4/o10gZmIVebDfMi8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=S7m0542l; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="S7m0542l" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A7E01C116C6; Tue, 3 Mar 2026 21:30:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772573434; bh=LHKfw1JsvUuXSzGaff7KKEjSDwosIwKtpx+tw1jAbBg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=S7m0542l7CX44oDBPFcTcWHY59+uBYCtpnYh8iT3LhmaSwFrcm59GOtVijhnEjUB9 986lo+De6LH74rlifiWpZffLJuL1YnZ2KH7QqyaLWcNJy8wnRTRAc54kWMxjLWgXyJ 2hKJj6J54VK2Ji8vvyeZW566RLjFB1Nra/Ag42P5Ir0ACSOdHQIzf1qgw7R884cmVm KOZaArQ7kr/f7X2dmX0MNbLB1X75EsEQSSd7C2Zy5jDl0Ifaydi13C2k+m1D95WZov cu8RgtOy/ZcEgt6AaFOpk1XEfk7hJNqA4JQNStK/ZVDmdF6VKXT30kFQig8FC2VH6P i+JO0/fpbwcbg== Date: Tue, 3 Mar 2026 14:30:27 -0700 From: Nathan Chancellor To: Thomas Gleixner Cc: LKML , Anna-Maria Behnsen , John Stultz , Stephen Boyd , Daniel Lezcano , Juri Lelli , Vincent Guittot , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , x86@kernel.org, Peter Zijlstra , Frederic Weisbecker , Eric Dumazet Subject: Re: [patch 20/48] x86/apic: Enable TSC coupled programming mode Message-ID: <20260303213027.GA2168957@ax162> References: <20260224163022.795809588@kernel.org> <20260224163430.076565985@kernel.org> <20260303012905.GA978396@ax162> <87jyvtyo6o.ffs@tglx> <20260303173809.GA1114907@ax162> <87ecm0zmsf.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87ecm0zmsf.ffs@tglx> On Tue, Mar 03, 2026 at 09:21:52PM +0100, Thomas Gleixner wrote: > On Tue, Mar 03 2026 at 10:38, Nathan Chancellor wrote: > > On Tue, Mar 03, 2026 at 03:37:03PM +0100, Thomas Gleixner wrote: > >> On Mon, Mar 02 2026 at 18:29, Nathan Chancellor wrote: > >> > > >> > After this change landed in -next as commit f246ec3478cf ("x86/apic: > >> > Enable TSC coupled programming mode"), two of my Intel-based test > >> > machines fail to boot. Unfortunately, I do not think I have any serial > >> > access on these, so I have little introspective ability. Is there any > >> > information I can provide or patches I can test to try and help figure > >> > out what is going on here? I have attached the output of lscpu of both > >> > machines, in case there is some common thread there. > >> > >> Grmbl. I stared at it for a while and I have a suspicion. Can you try > >> the patch below and also provide from one of the machines the output of > >> > >> dmesg | grep -i tsc > > > > This patch works on both machines, so your suspicion seemed spot on. > > > > Output of that dmesg commmand appears to be the same between > > 89f951a1e8ad and f246ec3478cf with that diff applied: > > > > [ 0.000000] tsc: Detected 2500.000 MHz processor > > [ 0.000000] tsc: Detected 2496.000 MHz TSC > > [ 0.008989] TSC deadline timer available > > [ 0.119139] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x23fa772cf26, max_idle_ns: 440795269835 ns > > [ 0.312141] clocksource: Switched to clocksource tsc-early > > [ 0.322686] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x23fa772cf26, max_idle_ns: 440795269835 ns > > [ 0.322951] clocksource: Switched to clocksource tsc > > Ha! That's exactly what I suspected. What happens is: > > TSC-early is installed, which is neither valid for high resolution > timers nor for coupled mode. A bit later TSC is installed with the same > frequency as TSC early. Which means the shift mult pair is not changing, > which then fails to invoke the update of maxns. That stays simply 0, so > the time is always armed for an event in the past and the machine dies > from TSC deadline timer interrupt storm. > > On all my test machines TSC frequency is refined against HPET and > installed late and that refinement always changes the shift/mult pair so > I never ran into this situation and obviously did not think about it > either. > > Let me write a proper change log and get this into the tip tree. > > Thanks for testing! No problem and thanks for the explanation! Unfortunately, in further testing, that diff appears to break booting my two AMD test systems, which had no problems with the current series. The output from that previous dmesg command from both systems on a vanilla next-20260303: [ 0.000000] tsc: Fast TSC calibration using PIT [ 0.000000] tsc: Detected 3792.761 MHz processor [ 0.061853] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x6d574392f2f, max_idle_ns: 881590904565 ns [ 0.332910] clocksource: Switched to clocksource tsc-early [ 1.368506] tsc: Refined TSC clocksource calibration: 3792.899 MHz [ 1.368521] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x6d584a46b0d, max_idle_ns: 881590977212 ns [ 1.368849] clocksource: Switched to clocksource tsc [ 4.497901] kvm_amd: TSC scaling supported [ 0.000000] tsc: Fast TSC calibration using PIT [ 0.000000] tsc: Detected 2994.309 MHz processor [ 0.179828] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x2b29459826f, max_idle_ns: 440795319985 ns [ 0.452947] clocksource: Switched to clocksource tsc-early [ 1.485796] tsc: Refined TSC clocksource calibration: 2994.372 MHz [ 1.485810] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x2b29812ce43, max_idle_ns: 440795323173 ns [ 1.486231] clocksource: Switched to clocksource tsc [ 7.870821] kvm_amd: TSC scaling supported Does it need to be conditionalized somehow? If there is any other information I can provide about these systems, please let me know. Cheers, Nathan