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Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" Subject: [PATCH 0/9] amd-pstate: Introduce AMD CPPC Performance Priority Date: Fri, 6 Mar 2026 15:27:44 +0530 Message-ID: <20260306095753.17155-1-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A2:EE_|CH3PR12MB8546:EE_ X-MS-Office365-Filtering-Correlation-Id: 6a8f5541-da5f-4fa9-fab4-08de7b66e4d4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|1800799024|13003099007; X-Microsoft-Antispam-Message-Info: HegMUtWtAmrbhU/JT+Wz+nuTs7PFaPsUDNiNK/k5B6qZJZH5OnoBpleIFEt0VxNogZHI3MDlP1kFlHZfDZZe8tgX+IXc08zY0ZEcyC41dYlCa75IqQBDqXhv1N16VqJdAhkkDzFJwe//HYLBT0xiHNK0j2NhNk/zSPvj3gEnoLuHuU3g3EY4rg1aplge1y+YD7e5dCUKs9tRQU6YWFcsOSQlQHLHjgZMIQRe5rUHdNgbOhc3CzP6NK2dwdkKOBrn3NPHOrG5y0AaWZYyxVhjCUtvIWIdgKpvUQkr+UrWqNm9a41sG0idw1YbnSan4zbzA8RzNafMueVpebha0plAboH/qkEhISOwyxCR/zSNqpq6x97pGcUJl/gfvMvc/GJDm1jMVhx7VSwaO5jaceOFjejPGKPnEMPE/6Xo0hEAI8E3Wtx3VOfxHSvAYAE1iUKT8Ac6TfQu3nTufzyrmLMBk1VYougx03Vo6cOi9Ox5UXczcI184yvUF8rCTHBq4HfQ33BYDQ9JAomR/5a6TuBFHDrYCW4NX6+k2MhOT6QwBN61feAQfU7Whk2VM1XnwGuUY0Unxm/LlOpPevenkqFCqtRFUvSBPZ2z9h9JE2rV+n76spTDWYbZUVyVqKapdTSNtlrFQbhIuY8A42W/DZL22MlAVFJh4On1fLH5UmDYiAY6UdMGSbMObKXay+TCsJ+maAgmf/lfYpZsvWCTVI+CSpvb4DvH5PS5G/4L3lykW5hVAs+j2I6EaXKkhjffdkWZLJi/+tghiob19uPtZBqOkQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(376014)(1800799024)(13003099007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: PFarPNiFJQbAaje3dl8ZfRwaQYANiMvaHMm302VPuipMfQcI1k27Kna2sgjjOysAy0z78DVZBzP/dDHNbMNY//ZYtM9+qg+CxlUN/JlS9hfQtPYlbKzjDsLdKo/HAY+3qW5/9vV4eGU3xuA0dC2fD2grvWbAptCJxaaVPmOinTnmr2oQ5+gnk8wc+URBvXiTK5Ad9K1LxfzJXWcDCEhbpq8RXFqIZplfA+j8u9Kz/1dOM5Fn4yJywcrPmi0Hraaa+frjWn7ZKpgLkMcj3RN8YXJ/los1kjYRyhXnt6e5J1NhPOb0kiGSS3FVQzuM0rfv0xpF2z9puIg21TwAlndY0Jv3qtm4T80oC36YbklmBX7uWFQQ1dQ3YYixHU3ZgGsN5/XqQFayWB06TD3EwCTnoThFZhl4FCiNtJYocgN8Mg8dhHj51BBop6kpLSuOb3tn X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2026 09:58:18.8810 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a8f5541-da5f-4fa9-fab4-08de7b66e4d4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8546 Hello, This patchset adds support to the amd-pstate driver for a for a new feature named "CPPC Performance Priority" that will be available on some of the future AMD processors. Details of the feature can be found in the AMD Publication titled "AMD64 Collaborative Processor Performance Control (CPPC) Performance Priority" (https://docs.amd.com/v/u/en-US/69206_1.10_AMD64_CPPC_PUB) Description: This feature allows userspace to specify different floor performance levels for different CPUs. The platform firmware takes these different floor performance levels into consideration while throttling the CPUs under power/thermal constraints. The presence of this feature is advertised through bit 16 of EDX register for CPUID leaf 0x80000007. The number of distinct floor performance levels supported on the platform will be advertised through the bits 32:39 of the MSR_AMD_CPPC_CAP1. Bits 0:7 of a new MSR MSR_AMD_CPPC_REQ2 (0xc00102b5) will be used to specify the desired floor performance level for that CPU. Key changes made by this patchset: * Fix a memory leak bug and a control-flow bug. * Plumb in proper visibility controls for the freq_attr attributes so that only relevant attributes can be made visible depending on the underlying platform and the current amd-pstate driver mode. * Add support for the new CPUID bits, the new MSR and parsing bits 32:39 of MSR_AMD_CPPC_CAP1. * Set the default value for MSR_AMD_CPPC_REQ2[0:7] (Floor perf) to CPPC.nominal_perf when the value at boot-time is lower than CPPC.lowest_perf * Add sysfs support for floor_freq and floor_count * Introduce a tracepoint trace_amd_pstate_cppc_req2 for tracking the updates to MSR_AMD_CPPC_REQ2. * Add documentation for amd_pstate_floor_{freq,count} Gautham R. Shenoy (9): amd-pstate: Fix memory leak in amd_pstate_epp_cpu_init() amd-pstate: Update cppc_req_cached in fast_switch case amd-pstate: Make certain freq_attrs conditionally visible x86/cpufeatures: Add AMD CPPC Performance Priority feature. amd-pstate: Add support for CPPC_REQ2 and FLOOR_PERF amd-pstate: Add sysfs support for floor_freq and floor_count amd-pstate: Introduce a tracepoint trace_amd_pstate_cppc_req2() Documentation/amd-pstate: List prefcore related sysfs files Documentation/amd-pstate: Add documentation for amd_pstate_floor_{freq,count} Documentation/admin-guide/pm/amd-pstate.rst | 47 +++- arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/include/asm/msr-index.h | 5 + arch/x86/kernel/cpu/scattered.c | 1 + drivers/cpufreq/amd-pstate-trace.h | 35 +++ drivers/cpufreq/amd-pstate.c | 267 +++++++++++++++++--- drivers/cpufreq/amd-pstate.h | 5 + tools/arch/x86/include/asm/cpufeatures.h | 2 +- 8 files changed, 324 insertions(+), 40 deletions(-) -- 2.34.1