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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 99ccyHUQ3qUgtiDTngNrDZferrnJGYyPZvM++QA5N/SPi22g2WCmM8GgX7iX9ws2H7LY0wMZoZxhwouF5zQRx223uR2aZOAiqLp5Ucf86CtaPAanM131DcRVAG27ooj2EkJqRS04Qo3TOMfodTvRn5lJ5q8xqhzEGeXp3zSlW6ogwEvjUnqK9YUyV2YkkZ7uWBJCsSrhV2PqYT+AvPGZoCZYJW4TBpm7FTy6Dr84nmDftAtAAXfvTozLNbrWKafxy5IhN4UtWZZwTNi0SGSWSiVIokPCWbjkSn+0p3w3M4icvyQQhQwmoK7DigOa1f3Dy7tVEca0HhcS1nY+QRww0dypiLZ8G0EHacyAs790lB5cBccffpeRz49ADqj0ZaAePejvbNDFcGmfw7H/zbMzcwKLjWl9LMaFPhh7F5l7queA6vY5z3WEwRgtt40+i+hL X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2026 17:46:07.1265 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1bd972eb-0bfd-4864-dd0e-08de7ba83ee3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8823 On Fri, 6 Mar 2026 08:00:15 +0000 wrote: > From: Srirangan Madhavan > > PCI: Add CXL DVSEC control, lock, and range register definitions > > Add register offset and field definitions for CXL DVSEC registers needed > by CXL state save/restore across resets: > > - CTRL2 (offset 0x10) and LOCK (offset 0x14) registers > - CONFIG_LOCK bit in the LOCK register > - RWL (read-write-when-locked) field masks for CTRL and range base > registers. > > Signed-off-by: Srirangan Madhavan > --- > include/uapi/linux/pci_regs.h | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index ec1c54b5a310..6fdc20d7f5e6 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -1353,14 +1353,20 @@ > #define PCI_DVSEC_CXL_HDM_COUNT __GENMASK(5, 4) > #define PCI_DVSEC_CXL_CTRL 0xC > #define PCI_DVSEC_CXL_MEM_ENABLE _BITUL(2) > +#define PCI_DVSEC_CXL_CTRL_RWL 0x5FED > +#define PCI_DVSEC_CXL_CTRL2 0x10 > +#define PCI_DVSEC_CXL_LOCK 0x14 > +#define PCI_DVSEC_CXL_LOCK_CONFIG _BITUL(0) > #define PCI_DVSEC_CXL_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10)) > #define PCI_DVSEC_CXL_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10)) > #define PCI_DVSEC_CXL_MEM_INFO_VALID _BITUL(0) > #define PCI_DVSEC_CXL_MEM_ACTIVE _BITUL(1) > #define PCI_DVSEC_CXL_MEM_SIZE_LOW __GENMASK(31, 28) > #define PCI_DVSEC_CXL_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10)) > +#define PCI_DVSEC_CXL_RANGE_BASE_HI_RWL 0xFFFFFFFF > #define PCI_DVSEC_CXL_RANGE_BASE_LOW(i) (0x24 + (i * 0x10)) > #define PCI_DVSEC_CXL_MEM_BASE_LOW __GENMASK(31, 28) > +#define PCI_DVSEC_CXL_RANGE_BASE_LO_RWL 0xF0000000 > > #define CXL_DVSEC_RANGE_MAX 2 > These RWL defines really seem to be more kernel policy than spec definitions. Do they really belong in the uAPI header? Thanks, Alex