From: Shawn Lin <shawn.lin@linux.dev>
To: Ulf Hansson <ulf.hansson@linaro.org>
Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
Shawn Lin <shawn.lin@linux.dev>
Subject: [PATCH 0/2] Validate and clean up UHS/DDR/HS200 timing checks
Date: Fri, 6 Mar 2026 20:48:10 +0800 [thread overview]
Message-ID: <20260306124812.332098-1-shawn.lin@linux.dev> (raw)
This series adds validation for UHS/DDR/HS200 timing modes when the host
only supports 1-bit bus width which also fixes a real performance drop issue
due to incorrect hs200 mode switch code. And then cleans up the check in
mmc_host_can_uhs().
Luke Wang (1):
mmc: core: Validate UHS/DDR/HS200 timing selection for 1-bit bus width
Shawn Lin (1):
mmc: core: Remove checking MMC_CAP_4_BIT_DATA from mmc_host_can_uhs()
drivers/mmc/core/host.c | 9 +++++++++
drivers/mmc/core/host.h | 6 +-----
2 files changed, 10 insertions(+), 5 deletions(-)
--
2.7.4
next reply other threads:[~2026-03-06 12:48 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-06 12:48 Shawn Lin [this message]
2026-03-06 12:48 ` [PATCH 1/2] mmc: core: Validate UHS/DDR/HS200 timing selection for 1-bit bus width Shawn Lin
2026-03-09 14:57 ` Ulf Hansson
2026-03-10 0:37 ` Shawn Lin
2026-03-06 12:48 ` [PATCH 2/2] mmc: core: Remove checking MMC_CAP_4_BIT_DATA from mmc_host_can_uhs() Shawn Lin
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