[PATCH 0/5] watchdog: rzn1: Add support for direct hardware reset

[PATCH 0/5] watchdog: rzn1: Add support for direct hardware reset

[Herve Codina (Schneider Electric)]

Hi,

The current watchdog driver handling wachdogs of the RZ/N1 SoCs is based
on interrupt only to perform the reset. On the watchdog timeout, an
interrupt is triggered and the software initiates the reset.

The watchdogs available in the RZ/N1 SoCs can directly perform an
hardware reset using their dedicated reset line.

On timeout, the watchdog also asserts its dedicated reset line. This
reset line is connected to the reset controller (part of sysctrl) and,
if this line is enabled as a possible reset source at the reset
controller level, it initiates a system reset.

This series adds support for this feature allowing watchdogs to directly
reset the system with any software needs when a watchdog timeout occurs.

The first two patches are minor fixes and improvements without changing
the current functional behavior.

Patches 3 to 5 add support for the feature adding:
  - The reset line description in the RZ/N1 watchdog binding,
  - A new helper at sysctrl level (sysctrl is handled by the clock
    driver in RZ/N1) to enable watchdog reset sources,
  - The support itself in the watchdog driver putting everything together.

Best regards,
Hervé

Herve Codina (Schneider Electric) (5):
  watchdog: rzn1: Fix reverse xmas tree declaration
  watchdog: rzn1: Use dev_err_probe()
  dt-bindings: watchdog: renesas,rzn1-wdt: Document the reset line
  clk: renesas: r9a06g032: Introduce a helper to set rsten register
  watchdog: rzn1: Add support for direct hardware reset

 .../bindings/watchdog/renesas,rzn1-wdt.yaml   | 22 +++++++
 drivers/clk/renesas/r9a06g032-clocks.c        | 32 ++++++++++
 drivers/watchdog/rzn1_wdt.c                   | 63 ++++++++++++++-----
 .../dt-bindings/watchdog/renesas,rzn1-wdt.h   | 16 +++++
 include/linux/soc/renesas/r9a06g032-sysctrl.h | 12 ++++
 5 files changed, 131 insertions(+), 14 deletions(-)
 create mode 100644 include/dt-bindings/watchdog/renesas,rzn1-wdt.h

-- 
2.53.0

[PATCH 1/5] watchdog: rzn1: Fix reverse xmas tree declaration

[Herve Codina (Schneider Electric)]

Variables declared in probe() don't follow the reverse xmas
tree convention.

Fix the declaration in order to follow the convention.

Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
---
 drivers/watchdog/rzn1_wdt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/watchdog/rzn1_wdt.c b/drivers/watchdog/rzn1_wdt.c
index 96fd04fbc2a2..b7034eac91d0 100644
--- a/drivers/watchdog/rzn1_wdt.c
+++ b/drivers/watchdog/rzn1_wdt.c
@@ -101,10 +101,10 @@ static const struct watchdog_ops rzn1_wdt_ops = {
 static int rzn1_wdt_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
-	struct rzn1_watchdog *wdt;
 	struct device_node *np = dev->of_node;
-	struct clk *clk;
+	struct rzn1_watchdog *wdt;
 	unsigned long clk_rate;
+	struct clk *clk;
 	int ret;
 	int irq;
 
-- 
2.53.0

[PATCH 2/5] watchdog: rzn1: Use dev_err_probe()

[Herve Codina (Schneider Electric)]

In the probe() function the following pattern is present several times:
	if (err) {
		dev_err(dev, ...);
		return err;
	}

Replace them by dev_err_probe() calls.

Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
---
 drivers/watchdog/rzn1_wdt.c | 18 ++++++------------
 1 file changed, 6 insertions(+), 12 deletions(-)

diff --git a/drivers/watchdog/rzn1_wdt.c b/drivers/watchdog/rzn1_wdt.c
index b7034eac91d0..98978b5cc5b4 100644
--- a/drivers/watchdog/rzn1_wdt.c
+++ b/drivers/watchdog/rzn1_wdt.c
@@ -122,22 +122,16 @@ static int rzn1_wdt_probe(struct platform_device *pdev)
 
 	ret = devm_request_irq(dev, irq, rzn1_wdt_irq, 0,
 			       np->name, wdt);
-	if (ret) {
-		dev_err(dev, "failed to request irq %d\n", irq);
-		return ret;
-	}
+	if (ret)
+		return dev_err_probe(dev, ret, "failed to request irq %d\n", irq);
 
 	clk = devm_clk_get_enabled(dev, NULL);
-	if (IS_ERR(clk)) {
-		dev_err(dev, "failed to get the clock\n");
-		return PTR_ERR(clk);
-	}
+	if (IS_ERR(clk))
+		return dev_err_probe(dev, PTR_ERR(clk), "failed to get the clock\n");
 
 	clk_rate = clk_get_rate(clk);
-	if (!clk_rate) {
-		dev_err(dev, "failed to get the clock rate\n");
-		return -EINVAL;
-	}
+	if (!clk_rate)
+		return dev_err_probe(dev, -EINVAL, "failed to get the clock\n");
 
 	wdt->clk_rate_khz = clk_rate / 1000;
 	wdt->wdtdev.info = &rzn1_wdt_info;
-- 
2.53.0

[PATCH 3/5] dt-bindings: watchdog: renesas,rzn1-wdt: Document the reset line

[Herve Codina (Schneider Electric)]

Watchdogs available in the RZ/N1 SoC can use their specific hardware
reset line to reset the system on watchdog timeout.

This line is not documented in the current binding.

Fill this lack and describe this per watchdog reset line.

Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
---
 .../bindings/watchdog/renesas,rzn1-wdt.yaml   | 22 +++++++++++++++++++
 .../dt-bindings/watchdog/renesas,rzn1-wdt.h   | 16 ++++++++++++++
 2 files changed, 38 insertions(+)
 create mode 100644 include/dt-bindings/watchdog/renesas,rzn1-wdt.h

diff --git a/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml
index 7e3ee533cd56..40a9a4ebc716 100644
--- a/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml
@@ -26,6 +26,26 @@ properties:
 
   timeout-sec: true
 
+  renesas,reset-line:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1]
+    description: |
+      The watchdog reset line (dt-bindings/watchdog/renesas,rzn1-wdt.h defines
+      these values). A wachdog timeout asserts this reset line to perform a
+      hardware system reset. Two watchdogs are present in the RZ/N1 SoC and
+      each of them has a dedicated reset line.
+
+        - 0: RZN1_WDT_A7_0
+          This reset line can be asserted only by the A7 0 watchdog. This
+          watchdog is the one mapped at 0x40008000 on RZ/N1 SoCs.
+
+        - 1: RZN1_WDT_A7_1
+          This reset line can be asserted only by the A7 1 watchdog. This
+          watchdog is the one mapped at 0x40009000 on RZ/N1 SoCs.
+
+      If the renesas,reset-line property is not present, the watchdog timeout
+      only triggers an interrupt.
+
 required:
   - compatible
   - reg
@@ -41,10 +61,12 @@ examples:
   - |
     #include <dt-bindings/clock/r9a06g032-sysctrl.h>
     #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/watchdog/renesas,rzn1-wdt.h>
 
     watchdog@40008000 {
             compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
             reg = <0x40008000 0x1000>;
             interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
             clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
+            renesas,reset-line = <RZN1_WDT_A7_0>;
     };
diff --git a/include/dt-bindings/watchdog/renesas,rzn1-wdt.h b/include/dt-bindings/watchdog/renesas,rzn1-wdt.h
new file mode 100644
index 000000000000..fe534aff0609
--- /dev/null
+++ b/include/dt-bindings/watchdog/renesas,rzn1-wdt.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * RZ/N1 watchdog reset lines
+ *
+ * Copyright (C) 2026 Bootlin
+ *
+ * Herve Codina <herve.codina@bootlin.com>
+ */
+
+#ifndef __DT_BINDINGS_RZN1_WDT_H__
+#define __DT_BINDINGS_RZN1_WDT_H__
+
+#define RZN1_WDT_A7_0		0
+#define RZN1_WDT_A7_1		1
+
+#endif /* __DT_BINDINGS_RZN1_WDT_H__ */
-- 
2.53.0

Re: [PATCH 3/5] dt-bindings: watchdog: renesas,rzn1-wdt: Document the reset line

[Krzysztof Kozlowski]

On 10/03/2026 18:32, Herve Codina (Schneider Electric) wrote:
> Watchdogs available in the RZ/N1 SoC can use their specific hardware
> reset line to reset the system on watchdog timeout.
> 
> This line is not documented in the current binding.
> 
> Fill this lack and describe this per watchdog reset line.
> 
> Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
> ---
>  .../bindings/watchdog/renesas,rzn1-wdt.yaml   | 22 +++++++++++++++++++
>  .../dt-bindings/watchdog/renesas,rzn1-wdt.h   | 16 ++++++++++++++
>  2 files changed, 38 insertions(+)
>  create mode 100644 include/dt-bindings/watchdog/renesas,rzn1-wdt.h
> 
> diff --git a/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml
> index 7e3ee533cd56..40a9a4ebc716 100644
> --- a/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml
> @@ -26,6 +26,26 @@ properties:
>  
>    timeout-sec: true
>  
> +  renesas,reset-line:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [0, 1]
> +    description: |
> +      The watchdog reset line (dt-bindings/watchdog/renesas,rzn1-wdt.h defines
> +      these values). A wachdog timeout asserts this reset line to perform a
> +      hardware system reset. Two watchdogs are present in the RZ/N1 SoC and
> +      each of them has a dedicated reset line.
> +
> +        - 0: RZN1_WDT_A7_0
> +          This reset line can be asserted only by the A7 0 watchdog. This
> +          watchdog is the one mapped at 0x40008000 on RZ/N1 SoCs.
> +
> +        - 1: RZN1_WDT_A7_1
> +          This reset line can be asserted only by the A7 1 watchdog. This
> +          watchdog is the one mapped at 0x40009000 on RZ/N1 SoCs.
> +
> +      If the renesas,reset-line property is not present, the watchdog timeout
> +      only triggers an interrupt.

I don't understand. You have two watchdogs (0x40008000 and 0x40009000)
so why you would tell each of them that they can reset line associated
with them? Can a watchdog reset other watchdog's line? No, thus code like:

watchdog@40008000 {
	renesas,reset-line = <RZN1_WDT_A7_1>;
};

makes no sense and thus is pointless to specify in DT.

What's more, if reset line is always wired (and how could it be since it
is fully within the soc), why would this be board-level property?



> +
>  required:
>    - compatible
>    - reg
> @@ -41,10 +61,12 @@ examples:
>    - |
>      #include <dt-bindings/clock/r9a06g032-sysctrl.h>
>      #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/watchdog/renesas,rzn1-wdt.h>
>  
>      watchdog@40008000 {
>              compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
>              reg = <0x40008000 0x1000>;
>              interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
>              clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
> +            renesas,reset-line = <RZN1_WDT_A7_0>;
>      };
> diff --git a/include/dt-bindings/watchdog/renesas,rzn1-wdt.h b/include/dt-bindings/watchdog/renesas,rzn1-wdt.h
> new file mode 100644
> index 000000000000..fe534aff0609
> --- /dev/null
> +++ b/include/dt-bindings/watchdog/renesas,rzn1-wdt.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * RZ/N1 watchdog reset lines
> + *
> + * Copyright (C) 2026 Bootlin
> + *
> + * Herve Codina <herve.codina@bootlin.com>
> + */
> +
> +#ifndef __DT_BINDINGS_RZN1_WDT_H__
> +#define __DT_BINDINGS_RZN1_WDT_H__
> +
> +#define RZN1_WDT_A7_0		0
> +#define RZN1_WDT_A7_1		1

I also see little value of the binding, but probably because I don't
understand the point of this patch.


Best regards,
Krzysztof

Re: [PATCH 3/5] dt-bindings: watchdog: renesas,rzn1-wdt: Document the reset line

[Herve Codina]

Hi Krzysztof,

On Tue, 10 Mar 2026 18:38:50 +0100
Krzysztof Kozlowski <krzk@kernel.org> wrote:

> On 10/03/2026 18:32, Herve Codina (Schneider Electric) wrote:
> > Watchdogs available in the RZ/N1 SoC can use their specific hardware
> > reset line to reset the system on watchdog timeout.
> > 
> > This line is not documented in the current binding.
> > 
> > Fill this lack and describe this per watchdog reset line.
> > 
> > Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
> > ---
> >  .../bindings/watchdog/renesas,rzn1-wdt.yaml   | 22 +++++++++++++++++++
> >  .../dt-bindings/watchdog/renesas,rzn1-wdt.h   | 16 ++++++++++++++
> >  2 files changed, 38 insertions(+)
> >  create mode 100644 include/dt-bindings/watchdog/renesas,rzn1-wdt.h
> > 
> > diff --git a/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml
> > index 7e3ee533cd56..40a9a4ebc716 100644
> > --- a/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml
> > +++ b/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml
> > @@ -26,6 +26,26 @@ properties:
> >  
> >    timeout-sec: true
> >  
> > +  renesas,reset-line:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [0, 1]
> > +    description: |
> > +      The watchdog reset line (dt-bindings/watchdog/renesas,rzn1-wdt.h defines
> > +      these values). A wachdog timeout asserts this reset line to perform a
> > +      hardware system reset. Two watchdogs are present in the RZ/N1 SoC and
> > +      each of them has a dedicated reset line.
> > +
> > +        - 0: RZN1_WDT_A7_0
> > +          This reset line can be asserted only by the A7 0 watchdog. This
> > +          watchdog is the one mapped at 0x40008000 on RZ/N1 SoCs.
> > +
> > +        - 1: RZN1_WDT_A7_1
> > +          This reset line can be asserted only by the A7 1 watchdog. This
> > +          watchdog is the one mapped at 0x40009000 on RZ/N1 SoCs.
> > +
> > +      If the renesas,reset-line property is not present, the watchdog timeout
> > +      only triggers an interrupt.  
> 
> I don't understand. You have two watchdogs (0x40008000 and 0x40009000)
> so why you would tell each of them that they can reset line associated
> with them? Can a watchdog reset other watchdog's line? No, thus code like:
> 
> watchdog@40008000 {
> 	renesas,reset-line = <RZN1_WDT_A7_1>;
> };
> 
> makes no sense and thus is pointless to specify in DT.
> 
> What's more, if reset line is always wired (and how could it be since it
> is fully within the soc), why would this be board-level property?

This is the exact same for interrupts and clocks.

Interrupts dedicated to IPs and hardwired, as well as clocks. Those resources
are described in DT.

Why not this reset line?

> 
> 
> 
> > +
> >  required:
> >    - compatible
> >    - reg
> > @@ -41,10 +61,12 @@ examples:
> >    - |
> >      #include <dt-bindings/clock/r9a06g032-sysctrl.h>
> >      #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/watchdog/renesas,rzn1-wdt.h>
> >  
> >      watchdog@40008000 {
> >              compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
> >              reg = <0x40008000 0x1000>;
> >              interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
> >              clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
> > +            renesas,reset-line = <RZN1_WDT_A7_0>;
> >      };
> > diff --git a/include/dt-bindings/watchdog/renesas,rzn1-wdt.h b/include/dt-bindings/watchdog/renesas,rzn1-wdt.h
> > new file mode 100644
> > index 000000000000..fe534aff0609
> > --- /dev/null
> > +++ b/include/dt-bindings/watchdog/renesas,rzn1-wdt.h
> > @@ -0,0 +1,16 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> > +/*
> > + * RZ/N1 watchdog reset lines
> > + *
> > + * Copyright (C) 2026 Bootlin
> > + *
> > + * Herve Codina <herve.codina@bootlin.com>
> > + */
> > +
> > +#ifndef __DT_BINDINGS_RZN1_WDT_H__
> > +#define __DT_BINDINGS_RZN1_WDT_H__
> > +
> > +#define RZN1_WDT_A7_0		0
> > +#define RZN1_WDT_A7_1		1  
> 
> I also see little value of the binding, but probably because I don't
> understand the point of this patch.

I mentioned 0 and 1 for those lines in the binding and referred to this
header. What's wrong with that ?

Clocks use the same kind of description.
A bunch of defines in header file to avoid a direct number.

Best regards,
Hervé

Re: [PATCH 3/5] dt-bindings: watchdog: renesas,rzn1-wdt: Document the reset line

[Krzysztof Kozlowski]

On 10/03/2026 19:12, Herve Codina wrote:
> Hi Krzysztof,
> 
> On Tue, 10 Mar 2026 18:38:50 +0100
> Krzysztof Kozlowski <krzk@kernel.org> wrote:
> 
>> On 10/03/2026 18:32, Herve Codina (Schneider Electric) wrote:
>>> Watchdogs available in the RZ/N1 SoC can use their specific hardware
>>> reset line to reset the system on watchdog timeout.
>>>
>>> This line is not documented in the current binding.
>>>
>>> Fill this lack and describe this per watchdog reset line.
>>>
>>> Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
>>> ---
>>>  .../bindings/watchdog/renesas,rzn1-wdt.yaml   | 22 +++++++++++++++++++
>>>  .../dt-bindings/watchdog/renesas,rzn1-wdt.h   | 16 ++++++++++++++
>>>  2 files changed, 38 insertions(+)
>>>  create mode 100644 include/dt-bindings/watchdog/renesas,rzn1-wdt.h
>>>
>>> diff --git a/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml
>>> index 7e3ee533cd56..40a9a4ebc716 100644
>>> --- a/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml
>>> +++ b/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml
>>> @@ -26,6 +26,26 @@ properties:
>>>  
>>>    timeout-sec: true
>>>  
>>> +  renesas,reset-line:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +    enum: [0, 1]
>>> +    description: |
>>> +      The watchdog reset line (dt-bindings/watchdog/renesas,rzn1-wdt.h defines
>>> +      these values). A wachdog timeout asserts this reset line to perform a
>>> +      hardware system reset. Two watchdogs are present in the RZ/N1 SoC and
>>> +      each of them has a dedicated reset line.
>>> +
>>> +        - 0: RZN1_WDT_A7_0
>>> +          This reset line can be asserted only by the A7 0 watchdog. This
>>> +          watchdog is the one mapped at 0x40008000 on RZ/N1 SoCs.
>>> +
>>> +        - 1: RZN1_WDT_A7_1
>>> +          This reset line can be asserted only by the A7 1 watchdog. This
>>> +          watchdog is the one mapped at 0x40009000 on RZ/N1 SoCs.
>>> +
>>> +      If the renesas,reset-line property is not present, the watchdog timeout
>>> +      only triggers an interrupt.  
>>
>> I don't understand. You have two watchdogs (0x40008000 and 0x40009000)
>> so why you would tell each of them that they can reset line associated
>> with them? Can a watchdog reset other watchdog's line? No, thus code like:
>>
>> watchdog@40008000 {
>> 	renesas,reset-line = <RZN1_WDT_A7_1>;
>> };
>>
>> makes no sense and thus is pointless to specify in DT.
>>
>> What's more, if reset line is always wired (and how could it be since it
>> is fully within the soc), why would this be board-level property?
> 
> This is the exact same for interrupts and clocks.
> 
> Interrupts dedicated to IPs and hardwired, as well as clocks. Those resources
> are described in DT.
> 
> Why not this reset line?

How is it the same? clocks and interrupts represent wiring between
modules, so that other module (provider) will be properly configured. So
where is here phandle to point to the other module which you are
configuring? How single number <0, 1> can be a phandle?


> 
>>
>>
>>
>>> +
>>>  required:
>>>    - compatible
>>>    - reg
>>> @@ -41,10 +61,12 @@ examples:
>>>    - |
>>>      #include <dt-bindings/clock/r9a06g032-sysctrl.h>
>>>      #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +    #include <dt-bindings/watchdog/renesas,rzn1-wdt.h>
>>>  
>>>      watchdog@40008000 {
>>>              compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
>>>              reg = <0x40008000 0x1000>;
>>>              interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
>>>              clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
>>> +            renesas,reset-line = <RZN1_WDT_A7_0>;
>>>      };
>>> diff --git a/include/dt-bindings/watchdog/renesas,rzn1-wdt.h b/include/dt-bindings/watchdog/renesas,rzn1-wdt.h
>>> new file mode 100644
>>> index 000000000000..fe534aff0609
>>> --- /dev/null
>>> +++ b/include/dt-bindings/watchdog/renesas,rzn1-wdt.h
>>> @@ -0,0 +1,16 @@
>>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>>> +/*
>>> + * RZ/N1 watchdog reset lines
>>> + *
>>> + * Copyright (C) 2026 Bootlin
>>> + *
>>> + * Herve Codina <herve.codina@bootlin.com>
>>> + */
>>> +
>>> +#ifndef __DT_BINDINGS_RZN1_WDT_H__
>>> +#define __DT_BINDINGS_RZN1_WDT_H__
>>> +
>>> +#define RZN1_WDT_A7_0		0
>>> +#define RZN1_WDT_A7_1		1  
>>
>> I also see little value of the binding, but probably because I don't
>> understand the point of this patch.
> 
> I mentioned 0 and 1 for those lines in the binding and referred to this
> header. What's wrong with that ?
> 
> Clocks use the same kind of description.
> A bunch of defines in header file to avoid a direct number.

So instead of answering my questions why you are doing this, why do you
need it, you use arguments "I saw some code looking like that, so I can
do that". No, you can not do that.

We don't copy blindly some code just because it looks similar. And we
avoid answering "I saw it somewhere" when someone asks you why you are
doing this.

Best regards,
Krzysztof

[PATCH 4/5] clk: renesas: r9a06g032: Introduce a helper to set rsten register

[Herve Codina (Schneider Electric)]

The rsten register is part of the system controller address range.

This register controls the reset sources allowed to reset the system.
Among them, watchdogs can be configured to be able to perform this
reset.

Introduce a new helper r9a06g032_sysctrl_enable_rst() in order to set
specific sources in the rsten register from the watchdog driver.

Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
---
 drivers/clk/renesas/r9a06g032-clocks.c        | 32 +++++++++++++++++++
 include/linux/soc/renesas/r9a06g032-sysctrl.h | 12 +++++++
 2 files changed, 44 insertions(+)

diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c
index 7407a4183a6c..517d46ff150e 100644
--- a/drivers/clk/renesas/r9a06g032-clocks.c
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -705,6 +705,38 @@ int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val)
 }
 EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_set_dmamux);
 
+int r9a06g032_sysctrl_enable_rst(enum r9a06g032_sysctrl_rst_src rst_src)
+{
+	unsigned long flags;
+	u32 rsten;
+	u32 val;
+
+	switch (rst_src) {
+	case R9A06G032_RST_WATCHDOG_CA7_0:
+		val = R9A06G032_SYSCTRL_WDA7RST_0;
+		break;
+
+	case R9A06G032_RST_WATCHDOG_CA7_1:
+		val = R9A06G032_SYSCTRL_WDA7RST_1;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (!sysctrl_priv)
+		return -EPROBE_DEFER;
+
+	spin_lock_irqsave(&sysctrl_priv->lock, flags);
+
+	rsten = readl(sysctrl_priv->reg + R9A06G032_SYSCTRL_RSTEN);
+	writel(rsten | val, sysctrl_priv->reg + R9A06G032_SYSCTRL_RSTEN);
+
+	spin_unlock_irqrestore(&sysctrl_priv->lock, flags);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_enable_rst);
+
 static void clk_rdesc_set(struct r9a06g032_priv *clocks,
 			  struct regbit rb, unsigned int on)
 {
diff --git a/include/linux/soc/renesas/r9a06g032-sysctrl.h b/include/linux/soc/renesas/r9a06g032-sysctrl.h
index 066dfb15cbdd..25542b49eb55 100644
--- a/include/linux/soc/renesas/r9a06g032-sysctrl.h
+++ b/include/linux/soc/renesas/r9a06g032-sysctrl.h
@@ -4,8 +4,20 @@
 
 #ifdef CONFIG_CLK_R9A06G032
 int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val);
+
+enum r9a06g032_sysctrl_rst_src {
+	R9A06G032_RST_WATCHDOG_CA7_0,
+	R9A06G032_RST_WATCHDOG_CA7_1,
+};
+
+int r9a06g032_sysctrl_enable_rst(enum r9a06g032_sysctrl_rst_src rst_src);
+
 #else
 static inline int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val) { return -ENODEV; }
+static inline int r9a06g032_sysctrl_enable_rst(enum r9a06g032_sysctrl_rst_src rst_src)
+{
+	return -ENODEV;
+}
 #endif
 
 #endif /* __LINUX_SOC_RENESAS_R9A06G032_SYSCTRL_H__ */
-- 
2.53.0

[PATCH 5/5] watchdog: rzn1: Add support for direct hardware reset

[Herve Codina (Schneider Electric)]

The watchdog timeout is signaled using an interrupt and, on this
interrupt, a software initiated reset is performed.

The watchdog is able to control directly the hardware reset without
any operation done by the interrupt handler. This feature allows the
watchdog to not depend on the software to reset the system when the
watchdog timeout occurs.

The 'renesas,reset-line' device-tree property has been recently
introduced in order to describe the hardware reset line used by the
watchdog on its timeout.

Handle this property in the driver and add support for the related
direct hardware reset.

Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
---
 drivers/watchdog/rzn1_wdt.c | 41 +++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/drivers/watchdog/rzn1_wdt.c b/drivers/watchdog/rzn1_wdt.c
index 98978b5cc5b4..bf623ea31be1 100644
--- a/drivers/watchdog/rzn1_wdt.c
+++ b/drivers/watchdog/rzn1_wdt.c
@@ -17,7 +17,9 @@
 #include <linux/of_irq.h>
 #include <linux/platform_device.h>
 #include <linux/reboot.h>
+#include <linux/soc/renesas/r9a06g032-sysctrl.h>
 #include <linux/watchdog.h>
+#include <dt-bindings/watchdog/renesas,rzn1-wdt.h>
 
 #define DEFAULT_TIMEOUT		60
 
@@ -98,6 +100,41 @@ static const struct watchdog_ops rzn1_wdt_ops = {
 	.ping = rzn1_wdt_ping,
 };
 
+static int rzn1_wdt_setup_rst_line(struct device *dev)
+{
+	enum r9a06g032_sysctrl_rst_src rst_src;
+	u32 reset_line;
+	int ret;
+
+	ret = of_property_read_u32(dev->of_node, "renesas,reset-line", &reset_line);
+	if (ret) {
+		if (ret == -EINVAL)
+			return 0; /* Property not present -> Ok, nothing to do */
+
+		return dev_err_probe(dev, ret, "Read 'renesas,reset-line' failed\n");
+	}
+
+	switch (reset_line) {
+	case RZN1_WDT_A7_0:
+		rst_src = R9A06G032_RST_WATCHDOG_CA7_0;
+		break;
+	case RZN1_WDT_A7_1:
+		rst_src = R9A06G032_RST_WATCHDOG_CA7_1;
+		break;
+
+	default:
+		return dev_err_probe(dev, -EINVAL,
+				     "Invalid 'renesas,reset-line' (%u)\n",
+				     reset_line);
+	}
+
+	ret = r9a06g032_sysctrl_enable_rst(rst_src);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to enable reset\n");
+
+	return 0;
+}
+
 static int rzn1_wdt_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -116,6 +153,10 @@ static int rzn1_wdt_probe(struct platform_device *pdev)
 	if (IS_ERR(wdt->base))
 		return PTR_ERR(wdt->base);
 
+	ret = rzn1_wdt_setup_rst_line(dev);
+	if (ret)
+		return ret;
+
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0)
 		return irq;
-- 
2.53.0

Re: [PATCH 5/5] watchdog: rzn1: Add support for direct hardware reset

[kernel test robot]

Hi Herve,

kernel test robot noticed the following build errors:

[auto build test ERROR on robh/for-next]
[also build test ERROR on geert-renesas-drivers/renesas-clk geert-renesas-devel/next groeck-staging/hwmon-next linus/master v7.0-rc3 next-20260310]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Herve-Codina-Schneider-Electric/watchdog-rzn1-Fix-reverse-xmas-tree-declaration/20260311-015157
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:    https://lore.kernel.org/r/20260310173249.161354-6-herve.codina%40bootlin.com
patch subject: [PATCH 5/5] watchdog: rzn1: Add support for direct hardware reset
config: arm-randconfig-002-20260311 (https://download.01.org/0day-ci/archive/20260311/202603111012.xhKbu8oc-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 8.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260311/202603111012.xhKbu8oc-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603111012.xhKbu8oc-lkp@intel.com/

All error/warnings (new ones prefixed by >>):

   In file included from drivers/watchdog/rzn1_wdt.c:20:
>> include/linux/soc/renesas/r9a06g032-sysctrl.h:17:53: warning: 'enum r9a06g032_sysctrl_rst_src' declared inside parameter list will not be visible outside of this definition or declaration
    static inline int r9a06g032_sysctrl_enable_rst(enum r9a06g032_sysctrl_rst_src rst_src)
                                                        ^~~~~~~~~~~~~~~~~~~~~~~~~
>> include/linux/soc/renesas/r9a06g032-sysctrl.h:17:79: error: parameter 1 ('rst_src') has incomplete type
    static inline int r9a06g032_sysctrl_enable_rst(enum r9a06g032_sysctrl_rst_src rst_src)
                                                   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
>> include/linux/soc/renesas/r9a06g032-sysctrl.h:17:19: error: function declaration isn't a prototype [-Werror=strict-prototypes]
    static inline int r9a06g032_sysctrl_enable_rst(enum r9a06g032_sysctrl_rst_src rst_src)
                      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/watchdog/rzn1_wdt.c: In function 'rzn1_wdt_setup_rst_line':
>> drivers/watchdog/rzn1_wdt.c:105:33: error: storage size of 'rst_src' isn't known
     enum r9a06g032_sysctrl_rst_src rst_src;
                                    ^~~~~~~
>> drivers/watchdog/rzn1_wdt.c:119:13: error: 'R9A06G032_RST_WATCHDOG_CA7_0' undeclared (first use in this function)
      rst_src = R9A06G032_RST_WATCHDOG_CA7_0;
                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/watchdog/rzn1_wdt.c:119:13: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/watchdog/rzn1_wdt.c:122:13: error: 'R9A06G032_RST_WATCHDOG_CA7_1' undeclared (first use in this function)
      rst_src = R9A06G032_RST_WATCHDOG_CA7_1;
                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/watchdog/rzn1_wdt.c:105:33: warning: unused variable 'rst_src' [-Wunused-variable]
     enum r9a06g032_sysctrl_rst_src rst_src;
                                    ^~~~~~~
   cc1: some warnings being treated as errors


vim +17 include/linux/soc/renesas/r9a06g032-sysctrl.h

21c34edbcc67b03 Herve Codina (Schneider Electric  2026-03-10  14) 
885525c1e7e27ea Miquel Raynal                     2022-04-27  15  #else
885525c1e7e27ea Miquel Raynal                     2022-04-27  16  static inline int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val) { return -ENODEV; }
21c34edbcc67b03 Herve Codina (Schneider Electric  2026-03-10 @17) static inline int r9a06g032_sysctrl_enable_rst(enum r9a06g032_sysctrl_rst_src rst_src)
21c34edbcc67b03 Herve Codina (Schneider Electric  2026-03-10  18) {
21c34edbcc67b03 Herve Codina (Schneider Electric  2026-03-10  19) 	return -ENODEV;
21c34edbcc67b03 Herve Codina (Schneider Electric  2026-03-10  20) }
885525c1e7e27ea Miquel Raynal                     2022-04-27  21  #endif
885525c1e7e27ea Miquel Raynal                     2022-04-27  22  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 5/5] watchdog: rzn1: Add support for direct hardware reset

[kernel test robot]

Hi Herve,

kernel test robot noticed the following build errors:

[auto build test ERROR on robh/for-next]
[also build test ERROR on geert-renesas-drivers/renesas-clk geert-renesas-devel/next groeck-staging/hwmon-next linus/master v7.0-rc3 next-20260310]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Herve-Codina-Schneider-Electric/watchdog-rzn1-Fix-reverse-xmas-tree-declaration/20260311-015157
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:    https://lore.kernel.org/r/20260310173249.161354-6-herve.codina%40bootlin.com
patch subject: [PATCH 5/5] watchdog: rzn1: Add support for direct hardware reset
config: x86_64-buildonly-randconfig-003-20260311 (https://download.01.org/0day-ci/archive/20260311/202603111437.eGpzXcOB-lkp@intel.com/config)
compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260311/202603111437.eGpzXcOB-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603111437.eGpzXcOB-lkp@intel.com/

All error/warnings (new ones prefixed by >>):

   In file included from drivers/watchdog/rzn1_wdt.c:20:
>> include/linux/soc/renesas/r9a06g032-sysctrl.h:17:53: warning: declaration of 'enum r9a06g032_sysctrl_rst_src' will not be visible outside of this function [-Wvisibility]
      17 | static inline int r9a06g032_sysctrl_enable_rst(enum r9a06g032_sysctrl_rst_src rst_src)
         |                                                     ^
>> include/linux/soc/renesas/r9a06g032-sysctrl.h:17:79: error: variable has incomplete type 'enum r9a06g032_sysctrl_rst_src'
      17 | static inline int r9a06g032_sysctrl_enable_rst(enum r9a06g032_sysctrl_rst_src rst_src)
         |                                                                               ^
   include/linux/soc/renesas/r9a06g032-sysctrl.h:17:53: note: forward declaration of 'enum r9a06g032_sysctrl_rst_src'
      17 | static inline int r9a06g032_sysctrl_enable_rst(enum r9a06g032_sysctrl_rst_src rst_src)
         |                                                     ^
>> drivers/watchdog/rzn1_wdt.c:105:33: error: variable has incomplete type 'enum r9a06g032_sysctrl_rst_src'
     105 |         enum r9a06g032_sysctrl_rst_src rst_src;
         |                                        ^
   drivers/watchdog/rzn1_wdt.c:105:7: note: forward declaration of 'enum r9a06g032_sysctrl_rst_src'
     105 |         enum r9a06g032_sysctrl_rst_src rst_src;
         |              ^
>> drivers/watchdog/rzn1_wdt.c:119:13: error: use of undeclared identifier 'R9A06G032_RST_WATCHDOG_CA7_0'
     119 |                 rst_src = R9A06G032_RST_WATCHDOG_CA7_0;
         |                           ^
>> drivers/watchdog/rzn1_wdt.c:122:13: error: use of undeclared identifier 'R9A06G032_RST_WATCHDOG_CA7_1'
     122 |                 rst_src = R9A06G032_RST_WATCHDOG_CA7_1;
         |                           ^
   1 warning and 4 errors generated.


vim +17 include/linux/soc/renesas/r9a06g032-sysctrl.h

21c34edbcc67b0 Herve Codina (Schneider Electric  2026-03-10  14) 
885525c1e7e27e Miquel Raynal                     2022-04-27  15  #else
885525c1e7e27e Miquel Raynal                     2022-04-27  16  static inline int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val) { return -ENODEV; }
21c34edbcc67b0 Herve Codina (Schneider Electric  2026-03-10 @17) static inline int r9a06g032_sysctrl_enable_rst(enum r9a06g032_sysctrl_rst_src rst_src)
21c34edbcc67b0 Herve Codina (Schneider Electric  2026-03-10  18) {
21c34edbcc67b0 Herve Codina (Schneider Electric  2026-03-10  19) 	return -ENODEV;
21c34edbcc67b0 Herve Codina (Schneider Electric  2026-03-10  20) }
885525c1e7e27e Miquel Raynal                     2022-04-27  21  #endif
885525c1e7e27e Miquel Raynal                     2022-04-27  22  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 0/5] watchdog: rzn1: Add support for direct hardware reset

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 1209 bytes --]

Hi Herve,

> On timeout, the watchdog also asserts its dedicated reset line. This
> reset line is connected to the reset controller (part of sysctrl) and,
> if this line is enabled as a possible reset source at the reset
> controller level, it initiates a system reset.

Okay, this seems similar to R-Car SoCs, so multiple things to add from
my side:

* I agree with Krzysztof that the renesas-vendor-binding is not the way
  to go. The information could be either deduced from the register range
  or you could have a link to the syscon describing somehow which reset
  to allow.

But:

* On R-Car, we require the firmware to correctly setup which resets are
  allowed. Only in cases of broken firmware, we override it in the
  system controller driver. The latter could probably be argued here.
  The firmware is old and will probably be not updated anymore.

* If the watchdog driver kind of unconditionally allows its own reset,
  we could keep it very simple and just unconditionally allow watchdog
  resets when probing the sysctrl driver?

* If you don't like this, you could also parse the DT for enabled
  watchdogs when probing the sysctrl driver and act upon findings?

Happy hacking,

   Wolfram


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH 0/5] watchdog: rzn1: Add support for direct hardware reset

[Herve Codina]

Hi Wolfram, Geert, Krzysztof

On Tue, 10 Mar 2026 22:53:01 +0100
Wolfram Sang <wsa+renesas@sang-engineering.com> wrote:

> Hi Herve,
> 
> > On timeout, the watchdog also asserts its dedicated reset line. This
> > reset line is connected to the reset controller (part of sysctrl) and,
> > if this line is enabled as a possible reset source at the reset
> > controller level, it initiates a system reset.  
> 
> Okay, this seems similar to R-Car SoCs, so multiple things to add from
> my side:
> 
> * I agree with Krzysztof that the renesas-vendor-binding is not the way
>   to go. The information could be either deduced from the register range
>   or you could have a link to the syscon describing somehow which reset
>   to allow.

I think deducing the information from the register range could be ok without
the need for introducing and use syscon.

On think that could be missing is the way to know if we are allowed or not
to enable this reset source.

Maybe a new "renesas,reset-type" property in the watchdog node could give
this information. This property could take the following value:
   - "soft":
     On timeout, the watchdog triggers an interrupt.

   - "hard":
     On timeout, the watchdog asserts the directly the system reset.

But I am not sure that this king of property will be accepted by Krzysztof
even if similar properties for similar features exist in other watchdog
bindings.

> 
> But:
> 
> * On R-Car, we require the firmware to correctly setup which resets are
>   allowed. Only in cases of broken firmware, we override it in the
>   system controller driver. The latter could probably be argued here.
>   The firmware is old and will probably be not updated anymore.
> 
> * If the watchdog driver kind of unconditionally allows its own reset,
>   we could keep it very simple and just unconditionally allow watchdog
>   resets when probing the sysctrl driver?
> 
> * If you don't like this, you could also parse the DT for enabled
>   watchdogs when probing the sysctrl driver and act upon findings?
> 

Looked deeper in the code.
On RZ/N1, the watchdog interrupt handler calls emergency_restart().

The clock driver (driver handling the sysctrl register area) allows the
software reset source unconditionally and register an handler to request
this software reset on system restart notification [1] and [2].

Whatever resets allowed by the firmware, it is already overridden for the
sofware reset and the watchdog resets the system.

So my plan for the next iteration is, as you suggested, unconditionally
allows watchdog resets in the clock driver probe(). Indeed it is the
driver in charge of sysctrl.

Geert any opinion on this topic?

[1] https://elixir.bootlin.com/linux/v7.0-rc1/source/drivers/clk/renesas/r9a06g032-clocks.c#L1346
[2] https://elixir.bootlin.com/linux/v7.0-rc1/source/drivers/clk/renesas/r9a06g032-clocks.c#L1282

Best regards,
Hervé

Re: [PATCH 0/5] watchdog: rzn1: Add support for direct hardware reset

[Wolfram Sang]

> On think that could be missing is the way to know if we are allowed or not
> to enable this reset source.
> 
> Maybe a new "renesas,reset-type" property in the watchdog node could give
> this information. This property could take the following value:
>    - "soft":
>      On timeout, the watchdog triggers an interrupt.
> 
>    - "hard":
>      On timeout, the watchdog asserts the directly the system reset.

This would be configuration, not HW description, so not for DT. Also, I
think watchdogs are expected to reset the system. I'd see it as a quirk
if they can only raise an interrupt. So, let's go the full system reset
route, I'd say.

> Whatever resets allowed by the firmware, it is already overridden for the
> sofware reset and the watchdog resets the system.

I see.

> So my plan for the next iteration is, as you suggested, unconditionally
> allows watchdog resets in the clock driver probe(). Indeed it is the
> driver in charge of sysctrl.

Sounds totally fine to me.

Happy hacking,

   Wolfram