[PATCH 0/2] reset: spacemit: k3: Decouple the composite reset

[PATCH 0/2] reset: spacemit: k3: Decouple the composite reset

[Yixun Lan]

Previously, the reset of The USB and PCIe was submited as a composite
reset, try to decouple them in this series.

The motivation behind is that it will will make the result more aligned
with the hardware which describe them as different reset lines, and also
match with the K3 dwc3 DT binding which request different reset, 
K1 and K3 SoC share same topology of the reset line design.

See the reset part info in binding doc
Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml

I've not added a Fixes tag here, as previous old reset ID has not been
used in any DTS, so it shouldn't cause any problem. I also mark
previous old reset ID as deprecated for now (let me know if it's ok).

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
Yixun Lan (2):
      dt-bindings: soc: spacemit: k3: Decouple composite reset lines
      reset: spacemit: k3: Add individual reset lines for USB, PCIe

 drivers/reset/spacemit/reset-spacemit-k3.c     | 50 +++++++++++++++-----------
 include/dt-bindings/reset/spacemit,k3-resets.h | 42 ++++++++++++++++------
 2 files changed, 62 insertions(+), 30 deletions(-)
---
base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
change-id: 20260312-01-k3-reset-usb-pci-dd00afa7561a

Best regards,
-- 
Yixun Lan <dlan@kernel.org>

[PATCH 1/2] dt-bindings: soc: spacemit: k3: Decouple composite reset lines

[Yixun Lan]

Instead of grouping several different reset lines into one composite
reset, decouple them to individual ones which make it more aligned
with underlying hardware.

The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC,
PHY. The PCIe controller also has three reset lines - DBI, Slave, Master.

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
 include/dt-bindings/reset/spacemit,k3-resets.h | 42 ++++++++++++++++++++------
 1 file changed, 32 insertions(+), 10 deletions(-)

diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h
index 79ac1c22b7b5..c12f8bd32047 100644
--- a/include/dt-bindings/reset/spacemit,k3-resets.h
+++ b/include/dt-bindings/reset/spacemit,k3-resets.h
@@ -97,11 +97,7 @@
 #define RESET_APMU_SDH0          13
 #define RESET_APMU_SDH1          14
 #define RESET_APMU_SDH2          15
-#define RESET_APMU_USB2          16
-#define RESET_APMU_USB3_PORTA    17
-#define RESET_APMU_USB3_PORTB    18
-#define RESET_APMU_USB3_PORTC    19
-#define RESET_APMU_USB3_PORTD    20
+/* Deprecated USB 16 - 20 */
 #define RESET_APMU_QSPI          21
 #define RESET_APMU_QSPI_BUS      22
 #define RESET_APMU_DMA           23
@@ -143,16 +139,42 @@
 #define RESET_APMU_UFS_ACLK      59
 #define RESET_APMU_EDP0          60
 #define RESET_APMU_EDP1          61
-#define RESET_APMU_PCIE_PORTA    62
-#define RESET_APMU_PCIE_PORTB    63
-#define RESET_APMU_PCIE_PORTC    64
-#define RESET_APMU_PCIE_PORTD    65
-#define RESET_APMU_PCIE_PORTE    66
+/* Deprecated PCIe 62 - 66 */
 #define RESET_APMU_EMAC0         67
 #define RESET_APMU_EMAC1         68
 #define RESET_APMU_EMAC2         69
 #define RESET_APMU_ESPI_MCLK     70
 #define RESET_APMU_ESPI_SCLK     71
+#define RESET_APMU_USB2_AHB      72
+#define RESET_APMU_USB2_VCC      73
+#define RESET_APMU_USB2_PHY      74
+#define RESET_APMU_USB3_A_AHB    75
+#define RESET_APMU_USB3_A_VCC    76
+#define RESET_APMU_USB3_A_PHY    77
+#define RESET_APMU_USB3_B_AHB    78
+#define RESET_APMU_USB3_B_VCC    79
+#define RESET_APMU_USB3_B_PHY    80
+#define RESET_APMU_USB3_C_AHB    81
+#define RESET_APMU_USB3_C_VCC    82
+#define RESET_APMU_USB3_C_PHY    83
+#define RESET_APMU_USB3_D_AHB    84
+#define RESET_APMU_USB3_D_VCC    85
+#define RESET_APMU_USB3_D_PHY    86
+#define RESET_APMU_PCIE_A_DBI    87
+#define RESET_APMU_PCIE_A_SLAVE  88
+#define RESET_APMU_PCIE_A_MASTER 89
+#define RESET_APMU_PCIE_B_DBI    90
+#define RESET_APMU_PCIE_B_SLAVE  91
+#define RESET_APMU_PCIE_B_MASTER 92
+#define RESET_APMU_PCIE_C_DBI    93
+#define RESET_APMU_PCIE_C_SLAVE  94
+#define RESET_APMU_PCIE_C_MASTER 95
+#define RESET_APMU_PCIE_D_DBI    96
+#define RESET_APMU_PCIE_D_SLAVE  97
+#define RESET_APMU_PCIE_D_MASTER 98
+#define RESET_APMU_PCIE_E_DBI    99
+#define RESET_APMU_PCIE_E_SLAVE  100
+#define RESET_APMU_PCIE_E_MASTER 101
 
 /* DCIU resets*/
 #define RESET_DCIU_HDMA          0

-- 
2.53.0

Re: [PATCH 1/2] dt-bindings: soc: spacemit: k3: Decouple composite reset lines

[Philipp Zabel]

On Do, 2026-03-12 at 10:34 +0000, Yixun Lan wrote:
> Instead of grouping several different reset lines into one composite
> reset, decouple them to individual ones which make it more aligned
> with underlying hardware.
>
> The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC,
> PHY. The PCIe controller also has three reset lines - DBI, Slave, Master.
> 
> Signed-off-by: Yixun Lan <dlan@kernel.org>
> ---
>  include/dt-bindings/reset/spacemit,k3-resets.h | 42 ++++++++++++++++++++------
>  1 file changed, 32 insertions(+), 10 deletions(-)
> 
> diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h
> index 79ac1c22b7b5..c12f8bd32047 100644
> --- a/include/dt-bindings/reset/spacemit,k3-resets.h
> +++ b/include/dt-bindings/reset/spacemit,k3-resets.h
> @@ -97,11 +97,7 @@
>  #define RESET_APMU_SDH0          13
>  #define RESET_APMU_SDH1          14
>  #define RESET_APMU_SDH2          15
> -#define RESET_APMU_USB2          16
> -#define RESET_APMU_USB3_PORTA    17
> -#define RESET_APMU_USB3_PORTB    18
> -#define RESET_APMU_USB3_PORTC    19
> -#define RESET_APMU_USB3_PORTD    20

This is backwards incompatible.
Are there any device trees using the APMU resets yet?
If not, I wonder if we should just renumber all APMU resets into a
contiguous range and try to get it into v7.0 as a fix.

Also, this breaks bisectability.
reset-spacemit-k3.c will fail to compile between patches 1 and 2.

regards
Philipp

Re: [PATCH 1/2] dt-bindings: soc: spacemit: k3: Decouple composite reset lines

[Yixun Lan]

Hi Philipp,

On 12:09 Thu 12 Mar     , Philipp Zabel wrote:
> On Do, 2026-03-12 at 10:34 +0000, Yixun Lan wrote:
> > Instead of grouping several different reset lines into one composite
> > reset, decouple them to individual ones which make it more aligned
> > with underlying hardware.
> >
> > The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC,
> > PHY. The PCIe controller also has three reset lines - DBI, Slave, Master.
> > 
> > Signed-off-by: Yixun Lan <dlan@kernel.org>
> > ---
> >  include/dt-bindings/reset/spacemit,k3-resets.h | 42 ++++++++++++++++++++------
> >  1 file changed, 32 insertions(+), 10 deletions(-)
> > 
> > diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h
> > index 79ac1c22b7b5..c12f8bd32047 100644
> > --- a/include/dt-bindings/reset/spacemit,k3-resets.h
> > +++ b/include/dt-bindings/reset/spacemit,k3-resets.h
> > @@ -97,11 +97,7 @@
> >  #define RESET_APMU_SDH0          13
> >  #define RESET_APMU_SDH1          14
> >  #define RESET_APMU_SDH2          15
> > -#define RESET_APMU_USB2          16
> > -#define RESET_APMU_USB3_PORTA    17
> > -#define RESET_APMU_USB3_PORTB    18
> > -#define RESET_APMU_USB3_PORTC    19
> > -#define RESET_APMU_USB3_PORTD    20
> 
> This is backwards incompatible.
> Are there any device trees using the APMU resets yet?
> If not, I wonder if we should just renumber all APMU resets into a
> contiguous range and try to get it into v7.0 as a fix.
> 
No, there is currently no consumers, so I could rework them into a contiguous
version, thanks for the suggestion

> Also, this breaks bisectability.
> reset-spacemit-k3.c will fail to compile between patches 1 and 2.
> 
I've tried a first version to squash the two patches, but got a checkpatch.pl complait
for binding should follow into a separate patch.

I can combine these two patches into one, is this Ok for you?

-- 
Yixun Lan (dlan)

Re: [PATCH 1/2] dt-bindings: soc: spacemit: k3: Decouple composite reset lines

[Conor Dooley]

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On Thu, Mar 12, 2026 at 07:28:58PM +0800, Yixun Lan wrote:
> Hi Philipp,
> 
> On 12:09 Thu 12 Mar     , Philipp Zabel wrote:
> > On Do, 2026-03-12 at 10:34 +0000, Yixun Lan wrote:
> > > Instead of grouping several different reset lines into one composite
> > > reset, decouple them to individual ones which make it more aligned
> > > with underlying hardware.
> > >
> > > The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC,
> > > PHY. The PCIe controller also has three reset lines - DBI, Slave, Master.
> > > 
> > > Signed-off-by: Yixun Lan <dlan@kernel.org>
> > > ---
> > >  include/dt-bindings/reset/spacemit,k3-resets.h | 42 ++++++++++++++++++++------
> > >  1 file changed, 32 insertions(+), 10 deletions(-)
> > > 
> > > diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h
> > > index 79ac1c22b7b5..c12f8bd32047 100644
> > > --- a/include/dt-bindings/reset/spacemit,k3-resets.h
> > > +++ b/include/dt-bindings/reset/spacemit,k3-resets.h
> > > @@ -97,11 +97,7 @@
> > >  #define RESET_APMU_SDH0          13
> > >  #define RESET_APMU_SDH1          14
> > >  #define RESET_APMU_SDH2          15
> > > -#define RESET_APMU_USB2          16
> > > -#define RESET_APMU_USB3_PORTA    17
> > > -#define RESET_APMU_USB3_PORTB    18
> > > -#define RESET_APMU_USB3_PORTC    19
> > > -#define RESET_APMU_USB3_PORTD    20
> > 
> > This is backwards incompatible.
> > Are there any device trees using the APMU resets yet?
> > If not, I wonder if we should just renumber all APMU resets into a
> > contiguous range and try to get it into v7.0 as a fix.
> > 
> No, there is currently no consumers, so I could rework them into a contiguous
> version, thanks for the suggestion

Only as long as it goes into 7.0, IMO, as a fix.

> > Also, this breaks bisectability.
> > reset-spacemit-k3.c will fail to compile between patches 1 and 2.
> > 
> I've tried a first version to squash the two patches, but got a checkpatch.pl complait
> for binding should follow into a separate patch.
> 
> I can combine these two patches into one, is this Ok for you?

Be very very very clear about why they're going together, otherwise you'll
get yelled at!

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Re: [PATCH 1/2] dt-bindings: soc: spacemit: k3: Decouple composite reset lines

[Yixun Lan]

Hi Conor,

On 17:30 Thu 12 Mar     , Conor Dooley wrote:
> On Thu, Mar 12, 2026 at 07:28:58PM +0800, Yixun Lan wrote:
> > Hi Philipp,
> > 
> > On 12:09 Thu 12 Mar     , Philipp Zabel wrote:
> > > On Do, 2026-03-12 at 10:34 +0000, Yixun Lan wrote:
> > > > Instead of grouping several different reset lines into one composite
> > > > reset, decouple them to individual ones which make it more aligned
> > > > with underlying hardware.
> > > >
> > > > The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC,
> > > > PHY. The PCIe controller also has three reset lines - DBI, Slave, Master.
> > > > 
> > > > Signed-off-by: Yixun Lan <dlan@kernel.org>
> > > > ---
> > > >  include/dt-bindings/reset/spacemit,k3-resets.h | 42 ++++++++++++++++++++------
> > > >  1 file changed, 32 insertions(+), 10 deletions(-)
> > > > 
> > > > diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h
> > > > index 79ac1c22b7b5..c12f8bd32047 100644
> > > > --- a/include/dt-bindings/reset/spacemit,k3-resets.h
> > > > +++ b/include/dt-bindings/reset/spacemit,k3-resets.h
> > > > @@ -97,11 +97,7 @@
> > > >  #define RESET_APMU_SDH0          13
> > > >  #define RESET_APMU_SDH1          14
> > > >  #define RESET_APMU_SDH2          15
> > > > -#define RESET_APMU_USB2          16
> > > > -#define RESET_APMU_USB3_PORTA    17
> > > > -#define RESET_APMU_USB3_PORTB    18
> > > > -#define RESET_APMU_USB3_PORTC    19
> > > > -#define RESET_APMU_USB3_PORTD    20
> > > 
> > > This is backwards incompatible.
> > > Are there any device trees using the APMU resets yet?
> > > If not, I wonder if we should just renumber all APMU resets into a
> > > contiguous range and try to get it into v7.0 as a fix.
> > > 
> > No, there is currently no consumers, so I could rework them into a contiguous
> > version, thanks for the suggestion
> 
> Only as long as it goes into 7.0, IMO, as a fix.
> 
Yes, that's the plan

In this case, I would change my mind to add a Fixes tag explicitly(shouldn't hurt!)

> > > Also, this breaks bisectability.
> > > reset-spacemit-k3.c will fail to compile between patches 1 and 2.
> > > 
> > I've tried a first version to squash the two patches, but got a checkpatch.pl complait
> > for binding should follow into a separate patch.
> > 
> > I can combine these two patches into one, is this Ok for you?
> 
> Be very very very clear about why they're going together, otherwise you'll
> get yelled at!
Ok, will add comment for this, thanks for the tip.

-- 
Yixun Lan (dlan)

Re: [PATCH 1/2] dt-bindings: soc: spacemit: k3: Decouple composite reset lines

[Philipp Zabel]

On Do, 2026-03-12 at 19:28 +0800, Yixun Lan wrote:
> Hi Philipp,
> 
> On 12:09 Thu 12 Mar     , Philipp Zabel wrote:
> > On Do, 2026-03-12 at 10:34 +0000, Yixun Lan wrote:
> > > Instead of grouping several different reset lines into one composite
> > > reset, decouple them to individual ones which make it more aligned
> > > with underlying hardware.
> > > 
> > > The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC,
> > > PHY. The PCIe controller also has three reset lines - DBI, Slave, Master.
> > > 
> > > Signed-off-by: Yixun Lan <dlan@kernel.org>
> > > ---
> > >  include/dt-bindings/reset/spacemit,k3-resets.h | 42 ++++++++++++++++++++------
> > >  1 file changed, 32 insertions(+), 10 deletions(-)
> > > 
> > > diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h
> > > index 79ac1c22b7b5..c12f8bd32047 100644
> > > --- a/include/dt-bindings/reset/spacemit,k3-resets.h
> > > +++ b/include/dt-bindings/reset/spacemit,k3-resets.h
> > > @@ -97,11 +97,7 @@
> > >  #define RESET_APMU_SDH0          13
> > >  #define RESET_APMU_SDH1          14
> > >  #define RESET_APMU_SDH2          15
> > > -#define RESET_APMU_USB2          16
> > > -#define RESET_APMU_USB3_PORTA    17
> > > -#define RESET_APMU_USB3_PORTB    18
> > > -#define RESET_APMU_USB3_PORTC    19
> > > -#define RESET_APMU_USB3_PORTD    20
> > 
> > This is backwards incompatible.
> > Are there any device trees using the APMU resets yet?
> > If not, I wonder if we should just renumber all APMU resets into a
> > contiguous range and try to get it into v7.0 as a fix.
> > 
> No, there is currently no consumers,

Good, that will make things easier.

> so I could rework them into a contiguous version, thanks for the suggestion
> 
> > Also, this breaks bisectability.
> > reset-spacemit-k3.c will fail to compile between patches 1 and 2.
> > 
> I've tried a first version to squash the two patches, but got a checkpatch.pl complait
> for binding should follow into a separate patch.
> 
> I can combine these two patches into one, is this Ok for you?

I'm in favor of fixing both the APMU defines and the only existing
user, the reset driver, in a single patch. Explain it well, add Fixes:
216e0a5e98e5 and 938ce3b16582 tags, and then I can apply it on the
reset/fixes branch in time for v7.0.

regards
Philipp

Re: [PATCH 1/2] dt-bindings: soc: spacemit: k3: Decouple composite reset lines

[Krzysztof Kozlowski]

On Thu, Mar 12, 2026 at 10:34:19AM +0000, Yixun Lan wrote:
> Instead of grouping several different reset lines into one composite
> reset, decouple them to individual ones which make it more aligned
> with underlying hardware.
> 
> The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC,
> PHY. The PCIe controller also has three reset lines - DBI, Slave, Master.

Either this is ABI break, which would need explanation, or it is not,
which also needs explanation and then fixing current bindings before
they are released.

Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: soc: spacemit: k3: Decouple composite reset lines

[Yixun Lan]

Hi Krzysztof, 

On 14:42 Fri 13 Mar     , Krzysztof Kozlowski wrote:
> On Thu, Mar 12, 2026 at 10:34:19AM +0000, Yixun Lan wrote:
> > Instead of grouping several different reset lines into one composite
> > reset, decouple them to individual ones which make it more aligned
> > with underlying hardware.
> > 
> > The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC,
> > PHY. The PCIe controller also has three reset lines - DBI, Slave, Master.
> 
> Either this is ABI break, which would need explanation, or it is not,
> which also needs explanation and then fixing current bindings before
> they are released.
> 
Literally, Changing IDs would result an ABI breakage, but since we have
no consumers - no driver/DT use those IDs so far, so we could safely
renumber it and push as a fix for it. This issue was already raised by
Philipp in this thread [1], and I agreeed, will put some explanations.

Link: https://lore.kernel.org/r/20260312112858-GKH302167@kernel.org [1]

-- 
Yixun Lan (dlan)

[PATCH 2/2] reset: spacemit: k3: Add individual reset lines for USB, PCIe

[Yixun Lan]

The DWC3 USB host controller in K3 SoC has three reset lines - AHB,
VCC, PHY. The PCIe controller also has three reset lines - DBI, Slave,
Master. So, decouple USB and PCIe reset line to individual ones.

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
 drivers/reset/spacemit/reset-spacemit-k3.c | 50 ++++++++++++++++++------------
 1 file changed, 30 insertions(+), 20 deletions(-)

diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c
index e9e32e4c1ba5..9f58526b0119 100644
--- a/drivers/reset/spacemit/reset-spacemit-k3.c
+++ b/drivers/reset/spacemit/reset-spacemit-k3.c
@@ -112,16 +112,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = {
 	[RESET_APMU_SDH0]	= RESET_DATA(APMU_SDH0_CLK_RES_CTRL,	0, BIT(1)),
 	[RESET_APMU_SDH1]	= RESET_DATA(APMU_SDH1_CLK_RES_CTRL,	0, BIT(1)),
 	[RESET_APMU_SDH2]	= RESET_DATA(APMU_SDH2_CLK_RES_CTRL,	0, BIT(1)),
-	[RESET_APMU_USB2]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0,
-				BIT(1)|BIT(2)|BIT(3)),
-	[RESET_APMU_USB3_PORTA]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0,
-				BIT(5)|BIT(6)|BIT(7)),
-	[RESET_APMU_USB3_PORTB]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0,
-				BIT(9)|BIT(10)|BIT(11)),
-	[RESET_APMU_USB3_PORTC]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0,
-				BIT(13)|BIT(14)|BIT(15)),
-	[RESET_APMU_USB3_PORTD]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0,
-				BIT(17)|BIT(18)|BIT(19)),
+	[RESET_APMU_USB2_AHB]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0, BIT(1)),
+	[RESET_APMU_USB2_VCC]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0, BIT(2)),
+	[RESET_APMU_USB2_PHY]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0, BIT(3)),
+	[RESET_APMU_USB3_A_AHB]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0, BIT(5)),
+	[RESET_APMU_USB3_A_VCC]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0, BIT(6)),
+	[RESET_APMU_USB3_A_PHY]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0, BIT(7)),
+	[RESET_APMU_USB3_B_AHB]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0, BIT(9)),
+	[RESET_APMU_USB3_B_VCC]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0, BIT(10)),
+	[RESET_APMU_USB3_B_PHY]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0, BIT(11)),
+	[RESET_APMU_USB3_C_AHB]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0, BIT(13)),
+	[RESET_APMU_USB3_C_VCC]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0, BIT(14)),
+	[RESET_APMU_USB3_C_PHY]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0, BIT(15)),
+	[RESET_APMU_USB3_D_AHB]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0, BIT(17)),
+	[RESET_APMU_USB3_D_VCC]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0, BIT(18)),
+	[RESET_APMU_USB3_D_PHY]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0, BIT(19)),
 	[RESET_APMU_QSPI]	= RESET_DATA(APMU_QSPI_CLK_RES_CTRL,	0, BIT(1)),
 	[RESET_APMU_QSPI_BUS]	= RESET_DATA(APMU_QSPI_CLK_RES_CTRL,	0, BIT(0)),
 	[RESET_APMU_DMA]	= RESET_DATA(APMU_DMA_CLK_RES_CTRL,	0, BIT(0)),
@@ -164,16 +169,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = {
 	[RESET_APMU_UFS_ACLK]	= RESET_DATA(APMU_UFS_CLK_RES_CTRL,	0, BIT(0)),
 	[RESET_APMU_EDP0]	= RESET_DATA(APMU_LCD_EDP_CTRL,		0, BIT(0)),
 	[RESET_APMU_EDP1]	= RESET_DATA(APMU_LCD_EDP_CTRL,		0, BIT(16)),
-	[RESET_APMU_PCIE_PORTA]	= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A,	0,
-				BIT(5) | BIT(4) | BIT(3)),
-	[RESET_APMU_PCIE_PORTB]	= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B,	0,
-				BIT(5) | BIT(4) | BIT(3)),
-	[RESET_APMU_PCIE_PORTC]	= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C,	0,
-				BIT(5) | BIT(4) | BIT(3)),
-	[RESET_APMU_PCIE_PORTD]	= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D,	0,
-				BIT(5) | BIT(4) | BIT(3)),
-	[RESET_APMU_PCIE_PORTE]	= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E,	0,
-				BIT(5) | BIT(4) | BIT(3)),
+	[RESET_APMU_PCIE_A_DBI]		= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A,	0, BIT(3)),
+	[RESET_APMU_PCIE_A_SLAVE]	= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A,	0, BIT(4)),
+	[RESET_APMU_PCIE_A_MASTER]	= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A,	0, BIT(5)),
+	[RESET_APMU_PCIE_B_DBI]		= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B,	0, BIT(3)),
+	[RESET_APMU_PCIE_B_SLAVE]	= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B,	0, BIT(4)),
+	[RESET_APMU_PCIE_B_MASTER]	= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B,	0, BIT(5)),
+	[RESET_APMU_PCIE_C_DBI]		= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C,	0, BIT(3)),
+	[RESET_APMU_PCIE_C_SLAVE]	= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C,	0, BIT(4)),
+	[RESET_APMU_PCIE_C_MASTER]	= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C,	0, BIT(5)),
+	[RESET_APMU_PCIE_D_DBI]		= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D,	0, BIT(3)),
+	[RESET_APMU_PCIE_D_SLAVE]	= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D,	0, BIT(4)),
+	[RESET_APMU_PCIE_D_MASTER]	= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D,	0, BIT(5)),
+	[RESET_APMU_PCIE_E_DBI]		= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E,	0, BIT(3)),
+	[RESET_APMU_PCIE_E_SLAVE]	= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E,	0, BIT(4)),
+	[RESET_APMU_PCIE_E_MASTER]	= RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E,	0, BIT(5)),
 	[RESET_APMU_EMAC0]	= RESET_DATA(APMU_EMAC0_CLK_RES_CTRL,	0, BIT(1)),
 	[RESET_APMU_EMAC1]	= RESET_DATA(APMU_EMAC1_CLK_RES_CTRL,	0, BIT(1)),
 	[RESET_APMU_EMAC2]	= RESET_DATA(APMU_EMAC2_CLK_RES_CTRL,	0, BIT(1)),

-- 
2.53.0

Re: [PATCH 2/2] reset: spacemit: k3: Add individual reset lines for USB, PCIe

[Philipp Zabel]

On Do, 2026-03-12 at 10:34 +0000, Yixun Lan wrote:
> The DWC3 USB host controller in K3 SoC has three reset lines - AHB,
> VCC, PHY. The PCIe controller also has three reset lines - DBI, Slave,
> Master. So, decouple USB and PCIe reset line to individual ones.
> 
> Signed-off-by: Yixun Lan <dlan@kernel.org>
> ---
>  drivers/reset/spacemit/reset-spacemit-k3.c | 50 ++++++++++++++++++------------
>  1 file changed, 30 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c
> index e9e32e4c1ba5..9f58526b0119 100644
> --- a/drivers/reset/spacemit/reset-spacemit-k3.c
> +++ b/drivers/reset/spacemit/reset-spacemit-k3.c
> @@ -112,16 +112,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = {
>  	[RESET_APMU_SDH0]	= RESET_DATA(APMU_SDH0_CLK_RES_CTRL,	0, BIT(1)),
>  	[RESET_APMU_SDH1]	= RESET_DATA(APMU_SDH1_CLK_RES_CTRL,	0, BIT(1)),
>  	[RESET_APMU_SDH2]	= RESET_DATA(APMU_SDH2_CLK_RES_CTRL,	0, BIT(1)),
> -	[RESET_APMU_USB2]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0,
> -				BIT(1)|BIT(2)|BIT(3)),
> -	[RESET_APMU_USB3_PORTA]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0,
> -				BIT(5)|BIT(6)|BIT(7)),
> -	[RESET_APMU_USB3_PORTB]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0,
> -				BIT(9)|BIT(10)|BIT(11)),
> -	[RESET_APMU_USB3_PORTC]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0,
> -				BIT(13)|BIT(14)|BIT(15)),
> -	[RESET_APMU_USB3_PORTD]	= RESET_DATA(APMU_USB_CLK_RES_CTRL,	0,
> -				BIT(17)|BIT(18)|BIT(19)),

If there are already APMU reset users around, these either need to stay
or the driver needs an of_xlate that makes sure the deprecated ranges
are never given out to consumers.

Or, if there are no RESET_APMU users whatsoever yet, we might be
allowed to renumber RESET_APMU_* into a contiguous range.


regards
Philipp