[PATCH 0/4] riscv: spacemit: k3: Add more resource to UART

[PATCH 0/4] riscv: spacemit: k3: Add more resource to UART

[Yixun Lan]

This series try to add more resource (clock, pinctrl, reset) to UART driver,
So it will not reply on external bootloader for initialization. While doing
this, I've tried to break these patchse into more fine pieces, adding clock,
pinctrl+gpio, reset separately, then UART.

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
Yixun Lan (4):
      riscv: dts: spacemit: k3: add clock tree
      riscv: dts: spacemit: k3: add pinctrl support
      riscv: dts: spacemit: k3: add GPIO support
      riscv: dts: spacemit: k3: add full resource to UART

 arch/riscv/boot/dts/spacemit/k3-pico-itx.dts |   3 +
 arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi |  24 +++++
 arch/riscv/boot/dts/spacemit/k3.dtsi         | 152 +++++++++++++++++++++++++--
 3 files changed, 169 insertions(+), 10 deletions(-)
---
base-commit: ec1fb4e55df47ed043ab2ccc6787e39b9d67e49b
change-id: 20260304-01-dts-uart-full-be53670773b5

Best regards,
-- 
Yixun Lan <dlan@kernel.org>

[PATCH 1/4] riscv: dts: spacemit: k3: add clock tree

[Yixun Lan]

Add clock support to SpacemiT K3 SoC, the clock tree consist of several
blocks which are APBC, APMU, DCIU, MPUM.

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
 arch/riscv/boot/dts/spacemit/k3.dtsi | 75 ++++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index b69cf81b5d55..e3d7f3102fd5 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -4,6 +4,7 @@
  * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
  */
 
+#include <dt-bindings/clock/spacemit,k3-clocks.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 /dts-v1/;
@@ -398,6 +399,36 @@ core3 {
 		};
 	};
 
+	clocks {
+		vctcxo_1m: clock-1m {
+			compatible = "fixed-clock";
+			clock-frequency = <1000000>;
+			clock-output-names = "vctcxo_1m";
+			#clock-cells = <0>;
+		};
+
+		vctcxo_24m: clock-24m {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "vctcxo_24m";
+			#clock-cells = <0>;
+		};
+
+		vctcxo_3m: clock-3m {
+			compatible = "fixed-clock";
+			clock-frequency = <3000000>;
+			clock-output-names = "vctcxo_3m";
+			#clock-cells = <0>;
+		};
+
+		osc_32k: clock-32k {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			clock-output-names = "osc_32k";
+			#clock-cells = <0>;
+		};
+	};
+
 	soc: soc {
 		compatible = "simple-bus";
 		interrupt-parent = <&saplic>;
@@ -406,6 +437,15 @@ soc: soc {
 		dma-noncoherent;
 		ranges;
 
+		syscon_apbc: system-controller@d4015000 {
+			compatible = "spacemit,k3-syscon-apbc";
+			reg = <0x0 0xd4015000 0x0 0x1000>;
+			clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
+			clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
 		uart0: serial@d4017000 {
 			compatible = "spacemit,k3-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017000 0x0 0x100>;
@@ -506,6 +546,41 @@ uart10: serial@d401f000 {
 			status = "disabled";
 		};
 
+		syscon_mpmu: system-controller@d4050000 {
+			compatible = "spacemit,k3-syscon-mpmu";
+			reg = <0x0 0xd4050000 0x0 0x10000>;
+			clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
+			clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
+			#clock-cells = <1>;
+			#power-domain-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		pll: clock-controller@d4090000 {
+			compatible = "spacemit,k3-pll";
+			reg = <0x0 0xd4090000 0x0 0x10000>;
+			clocks = <&vctcxo_24m>;
+			spacemit,mpmu = <&syscon_mpmu>;
+			#clock-cells = <1>;
+		};
+
+		syscon_apmu: system-controller@d4282800 {
+			compatible = "spacemit,k3-syscon-apmu";
+			reg = <0x0 0xd4282800 0x0 0x400>;
+			clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
+			clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
+			#clock-cells = <1>;
+			#power-domain-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		syscon_dciu: system-controller@d8440000 {
+			compatible = "spacemit,k3-syscon-dciu";
+			reg = <0x0 0xd8440000 0x0 0xc000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
 		simsic: interrupt-controller@e0400000 {
 			compatible = "spacemit,k3-imsics", "riscv,imsics";
 			reg = <0x0 0xe0400000 0x0 0x200000>;

-- 
2.53.0

Re: [PATCH 1/4] riscv: dts: spacemit: k3: add clock tree

[Samuel Holland]

Hi Yixun,

On 2026-03-04 1:36 AM, Yixun Lan wrote:
> Add clock support to SpacemiT K3 SoC, the clock tree consist of several
> blocks which are APBC, APMU, DCIU, MPUM.
> 
> Signed-off-by: Yixun Lan <dlan@kernel.org>
> ---
>  arch/riscv/boot/dts/spacemit/k3.dtsi | 75 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 75 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> index b69cf81b5d55..e3d7f3102fd5 100644
> --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> @@ -4,6 +4,7 @@
>   * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
>   */
>  
> +#include <dt-bindings/clock/spacemit,k3-clocks.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  
>  /dts-v1/;
> @@ -398,6 +399,36 @@ core3 {
>  		};
>  	};
>  
> +	clocks {
> +		vctcxo_1m: clock-1m {
> +			compatible = "fixed-clock";
> +			clock-frequency = <1000000>;
> +			clock-output-names = "vctcxo_1m";
> +			#clock-cells = <0>;
> +		};
> +
> +		vctcxo_24m: clock-24m {
> +			compatible = "fixed-clock";
> +			clock-frequency = <24000000>;
> +			clock-output-names = "vctcxo_24m";
> +			#clock-cells = <0>;
> +		};
> +
> +		vctcxo_3m: clock-3m {
> +			compatible = "fixed-clock";
> +			clock-frequency = <3000000>;
> +			clock-output-names = "vctcxo_3m";
> +			#clock-cells = <0>;
> +		};
> +
> +		osc_32k: clock-32k {
> +			compatible = "fixed-clock";
> +			clock-frequency = <32000>;
> +			clock-output-names = "osc_32k";
> +			#clock-cells = <0>;
> +		};

Are these clocks provided by SoC or by the board? Usually there's a crystal
external to the SoC that provides the root of the clock tree. If these clocks
are provided by the board, they (or at least the clock-frequency property)
should be in the board DT, not the SoC dtsi.

Also, the /clocks node is out of order.

Regards,
Samuel

> +	};
> +
>  	soc: soc {
>  		compatible = "simple-bus";
>  		interrupt-parent = <&saplic>;
> @@ -406,6 +437,15 @@ soc: soc {
>  		dma-noncoherent;
>  		ranges;
>  
> +		syscon_apbc: system-controller@d4015000 {
> +			compatible = "spacemit,k3-syscon-apbc";
> +			reg = <0x0 0xd4015000 0x0 0x1000>;
> +			clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
> +			clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
>  		uart0: serial@d4017000 {
>  			compatible = "spacemit,k3-uart", "intel,xscale-uart";
>  			reg = <0x0 0xd4017000 0x0 0x100>;
> @@ -506,6 +546,41 @@ uart10: serial@d401f000 {
>  			status = "disabled";
>  		};
>  
> +		syscon_mpmu: system-controller@d4050000 {
> +			compatible = "spacemit,k3-syscon-mpmu";
> +			reg = <0x0 0xd4050000 0x0 0x10000>;
> +			clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
> +			clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
> +			#clock-cells = <1>;
> +			#power-domain-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
> +		pll: clock-controller@d4090000 {
> +			compatible = "spacemit,k3-pll";
> +			reg = <0x0 0xd4090000 0x0 0x10000>;
> +			clocks = <&vctcxo_24m>;
> +			spacemit,mpmu = <&syscon_mpmu>;
> +			#clock-cells = <1>;
> +		};
> +
> +		syscon_apmu: system-controller@d4282800 {
> +			compatible = "spacemit,k3-syscon-apmu";
> +			reg = <0x0 0xd4282800 0x0 0x400>;
> +			clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
> +			clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
> +			#clock-cells = <1>;
> +			#power-domain-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
> +		syscon_dciu: system-controller@d8440000 {
> +			compatible = "spacemit,k3-syscon-dciu";
> +			reg = <0x0 0xd8440000 0x0 0xc000>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
>  		simsic: interrupt-controller@e0400000 {
>  			compatible = "spacemit,k3-imsics", "riscv,imsics";
>  			reg = <0x0 0xe0400000 0x0 0x200000>;
> 

Re: [PATCH 1/4] riscv: dts: spacemit: k3: add clock tree

[Yixun Lan]

Hi Samuel,

On 20:44 Fri 13 Mar     , Samuel Holland wrote:
> Hi Yixun,
> 
> On 2026-03-04 1:36 AM, Yixun Lan wrote:
> > Add clock support to SpacemiT K3 SoC, the clock tree consist of several
> > blocks which are APBC, APMU, DCIU, MPUM.
> > 
> > Signed-off-by: Yixun Lan <dlan@kernel.org>
> > ---
> >  arch/riscv/boot/dts/spacemit/k3.dtsi | 75 ++++++++++++++++++++++++++++++++++++
> >  1 file changed, 75 insertions(+)
> > 
> > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > index b69cf81b5d55..e3d7f3102fd5 100644
> > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > @@ -4,6 +4,7 @@
> >   * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
> >   */
> >  
> > +#include <dt-bindings/clock/spacemit,k3-clocks.h>
> >  #include <dt-bindings/interrupt-controller/irq.h>
> >  
> >  /dts-v1/;
> > @@ -398,6 +399,36 @@ core3 {
> >  		};
> >  	};
> >  
> > +	clocks {
> > +		vctcxo_1m: clock-1m {
> > +			compatible = "fixed-clock";
> > +			clock-frequency = <1000000>;
> > +			clock-output-names = "vctcxo_1m";
> > +			#clock-cells = <0>;
> > +		};
> > +
> > +		vctcxo_24m: clock-24m {
> > +			compatible = "fixed-clock";
> > +			clock-frequency = <24000000>;
> > +			clock-output-names = "vctcxo_24m";
> > +			#clock-cells = <0>;
> > +		};
> > +
> > +		vctcxo_3m: clock-3m {
> > +			compatible = "fixed-clock";
> > +			clock-frequency = <3000000>;
> > +			clock-output-names = "vctcxo_3m";
> > +			#clock-cells = <0>;
> > +		};
> > +
> > +		osc_32k: clock-32k {
> > +			compatible = "fixed-clock";
> > +			clock-frequency = <32000>;
> > +			clock-output-names = "osc_32k";
> > +			#clock-cells = <0>;
> > +		};
> 
> Are these clocks provided by SoC or by the board? Usually there's a crystal
> external to the SoC that provides the root of the clock tree. If these clocks
> are provided by the board, they (or at least the clock-frequency property)
> should be in the board DT, not the SoC dtsi.
> 
It's true, as a quick check, osc_32k provided by P1 PMU, while vctcxo_24m is
a crystal, vctcxo_1m and vctcxo_3m are also marked as external in the clock
tree, but I would confirm them later..

I agree to move them out of SoC dtsi file - k3.dtsi, while due to all boards share
the same clock topology, what if I creating a k3-clock.dtsi and making it shared 
between all board dts file? to avoid massive DTS duplication

> Also, the /clocks node is out of order.
> 
I will move osc_32k before vtccxo_1m, assuming it's the problem you
refered to?

> Regards,
> Samuel

-- 
Yixun Lan (dlan)

Re: [PATCH 1/4] riscv: dts: spacemit: k3: add clock tree

[Samuel Holland]

Hi Yixun,

On 2026-03-14 3:52 AM, Yixun Lan wrote:
> On 20:44 Fri 13 Mar     , Samuel Holland wrote:
>> On 2026-03-04 1:36 AM, Yixun Lan wrote:
>>> Add clock support to SpacemiT K3 SoC, the clock tree consist of several
>>> blocks which are APBC, APMU, DCIU, MPUM.
>>>
>>> Signed-off-by: Yixun Lan <dlan@kernel.org>
>>> ---
>>>  arch/riscv/boot/dts/spacemit/k3.dtsi | 75 ++++++++++++++++++++++++++++++++++++
>>>  1 file changed, 75 insertions(+)
>>>
>>> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
>>> index b69cf81b5d55..e3d7f3102fd5 100644
>>> --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
>>> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
>>> @@ -4,6 +4,7 @@
>>>   * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
>>>   */
>>>  
>>> +#include <dt-bindings/clock/spacemit,k3-clocks.h>
>>>  #include <dt-bindings/interrupt-controller/irq.h>
>>>  
>>>  /dts-v1/;
>>> @@ -398,6 +399,36 @@ core3 {
>>>  		};
>>>  	};
>>>  
>>> +	clocks {
>>> +		vctcxo_1m: clock-1m {
>>> +			compatible = "fixed-clock";
>>> +			clock-frequency = <1000000>;
>>> +			clock-output-names = "vctcxo_1m";
>>> +			#clock-cells = <0>;
>>> +		};
>>> +
>>> +		vctcxo_24m: clock-24m {
>>> +			compatible = "fixed-clock";
>>> +			clock-frequency = <24000000>;
>>> +			clock-output-names = "vctcxo_24m";
>>> +			#clock-cells = <0>;
>>> +		};
>>> +
>>> +		vctcxo_3m: clock-3m {
>>> +			compatible = "fixed-clock";
>>> +			clock-frequency = <3000000>;
>>> +			clock-output-names = "vctcxo_3m";
>>> +			#clock-cells = <0>;
>>> +		};
>>> +
>>> +		osc_32k: clock-32k {
>>> +			compatible = "fixed-clock";
>>> +			clock-frequency = <32000>;
>>> +			clock-output-names = "osc_32k";
>>> +			#clock-cells = <0>;
>>> +		};
>>
>> Are these clocks provided by SoC or by the board? Usually there's a crystal
>> external to the SoC that provides the root of the clock tree. If these clocks
>> are provided by the board, they (or at least the clock-frequency property)
>> should be in the board DT, not the SoC dtsi.
>>
> It's true, as a quick check, osc_32k provided by P1 PMU, while vctcxo_24m is
> a crystal, vctcxo_1m and vctcxo_3m are also marked as external in the clock
> tree, but I would confirm them later..

In that case, osc_32k should ideally be a reference to the P1 PMU clock
provider, not a fixed-clock. But this may be infeasible if it creates dependency
loops (PMU depends on I2C, I2C depends on clocks, clocks depend on PMU).

> I agree to move them out of SoC dtsi file - k3.dtsi, while due to all boards share
> the same clock topology, what if I creating a k3-clock.dtsi and making it shared 
> between all board dts file? to avoid massive DTS duplication

Yes, it is common practice to create a .dtsi file for things shared among
several boards for a SoC (for example if they are all based on a reference
platform). You may want to name it something more generic if more than just
clocks can be shared (like k3-common.dtsi, compare jh7110-common.dtsi).

>> Also, the /clocks node is out of order.
>>
> I will move osc_32k before vtccxo_1m, assuming it's the problem you
> refered to?

I mean that /clocks sorts alphabetically before /cpus. Your ordering of the
fixed-clocks nodes themselves is fine.

Regards,
Samuel

Re: [PATCH 1/4] riscv: dts: spacemit: k3: add clock tree

[Yixun Lan]

Hi Samuel,

On 09:13 Sat 14 Mar     , Samuel Holland wrote:
> Hi Yixun,
> 
> On 2026-03-14 3:52 AM, Yixun Lan wrote:
> > On 20:44 Fri 13 Mar     , Samuel Holland wrote:
> >> On 2026-03-04 1:36 AM, Yixun Lan wrote:
> >>> Add clock support to SpacemiT K3 SoC, the clock tree consist of several
> >>> blocks which are APBC, APMU, DCIU, MPUM.
> >>>
> >>> Signed-off-by: Yixun Lan <dlan@kernel.org>
> >>> ---
> >>>  arch/riscv/boot/dts/spacemit/k3.dtsi | 75 ++++++++++++++++++++++++++++++++++++
> >>>  1 file changed, 75 insertions(+)
> >>>
> >>> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> >>> index b69cf81b5d55..e3d7f3102fd5 100644
> >>> --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> >>> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> >>> @@ -4,6 +4,7 @@
> >>>   * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
> >>>   */
> >>>  
> >>> +#include <dt-bindings/clock/spacemit,k3-clocks.h>
> >>>  #include <dt-bindings/interrupt-controller/irq.h>
> >>>  
> >>>  /dts-v1/;
> >>> @@ -398,6 +399,36 @@ core3 {
> >>>  		};
> >>>  	};
> >>>  
> >>> +	clocks {
> >>> +		vctcxo_1m: clock-1m {
> >>> +			compatible = "fixed-clock";
> >>> +			clock-frequency = <1000000>;
> >>> +			clock-output-names = "vctcxo_1m";
> >>> +			#clock-cells = <0>;
> >>> +		};
> >>> +
> >>> +		vctcxo_24m: clock-24m {
> >>> +			compatible = "fixed-clock";
> >>> +			clock-frequency = <24000000>;
> >>> +			clock-output-names = "vctcxo_24m";
> >>> +			#clock-cells = <0>;
> >>> +		};
> >>> +
> >>> +		vctcxo_3m: clock-3m {
> >>> +			compatible = "fixed-clock";
> >>> +			clock-frequency = <3000000>;
> >>> +			clock-output-names = "vctcxo_3m";
> >>> +			#clock-cells = <0>;
> >>> +		};
> >>> +
> >>> +		osc_32k: clock-32k {
> >>> +			compatible = "fixed-clock";
> >>> +			clock-frequency = <32000>;
> >>> +			clock-output-names = "osc_32k";
> >>> +			#clock-cells = <0>;
> >>> +		};
> >>
> >> Are these clocks provided by SoC or by the board? Usually there's a crystal
> >> external to the SoC that provides the root of the clock tree. If these clocks
> >> are provided by the board, they (or at least the clock-frequency property)
> >> should be in the board DT, not the SoC dtsi.
> >>
> > It's true, as a quick check, osc_32k provided by P1 PMU, while vctcxo_24m is
> > a crystal, vctcxo_1m and vctcxo_3m are also marked as external in the clock
> > tree, but I would confirm them later..
> 
> In that case, osc_32k should ideally be a reference to the P1 PMU clock
> provider, not a fixed-clock. But this may be infeasible if it creates dependency
> loops (PMU depends on I2C, I2C depends on clocks, clocks depend on PMU).
> 
Yes, in an ideal case, not only there is dependency loop, but need to
implement a clock tree for P1..

Currently, I'd leave it as fixed-clock as is, since the 32k clock is
always on from P1 since power up

Also, for vctcxo_1m and vctcxo_3m, they are clocks derived from vctcxo_24m which
unable to be gate off, so I think it's ok to leave them as fixed-clock.

> > I agree to move them out of SoC dtsi file - k3.dtsi, while due to all boards share
> > the same clock topology, what if I creating a k3-clock.dtsi and making it shared 
> > between all board dts file? to avoid massive DTS duplication
> 
> Yes, it is common practice to create a .dtsi file for things shared among
> several boards for a SoC (for example if they are all based on a reference
> platform). You may want to name it something more generic if more than just
> clocks can be shared (like k3-common.dtsi, compare jh7110-common.dtsi).
> 
k3-common.dtsi sounds good to me

> >> Also, the /clocks node is out of order.
> >>
> > I will move osc_32k before vtccxo_1m, assuming it's the problem you
> > refered to?
> 
> I mean that /clocks sorts alphabetically before /cpus. Your ordering of the
> fixed-clocks nodes themselves is fine.
> 
ok, I got

> Regards,
> Samuel
> 
> 

-- 
Yixun Lan (dlan)

[PATCH 2/4] riscv: dts: spacemit: k3: add pinctrl support

[Yixun Lan]

Populate pinctrl node in Device Tree for SpacemiT K3 SoC, So devices
can request pinctrl resource properly.

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
 arch/riscv/boot/dts/spacemit/k3.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index e3d7f3102fd5..6449ab056293 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -536,6 +536,14 @@ uart9: serial@d4017800 {
 			status = "disabled";
 		};
 
+		pinctrl: pinctrl@d401e000 {
+			compatible = "spacemit,k3-pinctrl";
+			reg = <0x0 0xd401e000 0x0 0x1000>;
+			clocks = <&syscon_apbc CLK_APBC_AIB>,
+				 <&syscon_apbc CLK_APBC_AIB_BUS>;
+			clock-names = "func", "bus";
+		};
+
 		uart10: serial@d401f000 {
 			compatible = "spacemit,k3-uart", "intel,xscale-uart";
 			reg = <0x0 0xd401f000 0x0 0x100>;

-- 
2.53.0

[PATCH 3/4] riscv: dts: spacemit: k3: add GPIO support

[Yixun Lan]

Add GPIO node in the Device Tree, so devices are able to request GPIO
resource properly.

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
 arch/riscv/boot/dts/spacemit/k3.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index 6449ab056293..3683a1a65362 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -536,6 +536,24 @@ uart9: serial@d4017800 {
 			status = "disabled";
 		};
 
+		gpio: gpio@d4019000 {
+			compatible = "spacemit,k3-gpio";
+			reg = <0x0 0xd4019000 0x0 0x100>;
+			clocks = <&syscon_apbc CLK_APBC_GPIO>,
+				 <&syscon_apbc CLK_APBC_GPIO_BUS>;
+			clock-names = "core", "bus";
+			gpio-controller;
+			#gpio-cells = <3>;
+			interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&saplic>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			gpio-ranges = <&pinctrl 0 0 0 32>,
+				      <&pinctrl 1 0 32 32>,
+				      <&pinctrl 2 0 64 32>,
+				      <&pinctrl 3 0 96 32>;
+		};
+
 		pinctrl: pinctrl@d401e000 {
 			compatible = "spacemit,k3-pinctrl";
 			reg = <0x0 0xd401e000 0x0 0x1000>;

-- 
2.53.0

[PATCH 4/4] riscv: dts: spacemit: k3: add full resource to UART

[Yixun Lan]

Previously the UART rely on external bootloader to initialize clock,
pinctrl and reset, to solve this, explicitly adding those resource in
Device Tree, so UART driver will handle them properly.

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
 arch/riscv/boot/dts/spacemit/k3-pico-itx.dts |  3 ++
 arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 24 +++++++++++++
 arch/riscv/boot/dts/spacemit/k3.dtsi         | 51 ++++++++++++++++++++++------
 3 files changed, 68 insertions(+), 10 deletions(-)

diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
index b691304d4b74..b098dbd0e7a1 100644
--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
@@ -5,6 +5,7 @@
  */
 
 #include "k3.dtsi"
+#include "k3-pinctrl.dtsi"
 
 / {
 	model = "SpacemiT K3 Pico-ITX";
@@ -25,5 +26,7 @@ memory@100000000 {
 };
 
 &uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_0_cfg>;
 	status = "okay";
 };
diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
new file mode 100644
index 000000000000..efb0f1572188
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2026 Yixun Lan <dlan@kernel.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#define K3_PADCONF(pin, func) (((pin) << 16) | (func))
+
+/* Map GPIO pin to each bank's <index, offset> */
+#define K3_GPIO(x)	(x / 32) (x % 32)
+
+&pinctrl {
+	/omit-if-no-ref/
+	uart0_0_cfg: uart0-0-cfg {
+		uart0-0-pins {
+			pinmux = <K3_PADCONF(149, 2)>,	/* uart0 tx */
+				 <K3_PADCONF(150, 2)>;	/* uart0 rx */
+
+			bias-pull-up = <0>;
+			drive-strength = <25>;
+		};
+	};
+};
diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index 3683a1a65362..a3a8ceddabec 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include <dt-bindings/clock/spacemit,k3-clocks.h>
+#include <dt-bindings/reset/spacemit,k3-resets.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 /dts-v1/;
@@ -451,7 +452,10 @@ uart0: serial@d4017000 {
 			reg = <0x0 0xd4017000 0x0 0x100>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clock-frequency = <14700000>;
+			clocks = <&syscon_apbc CLK_APBC_UART0>,
+				 <&syscon_apbc CLK_APBC_UART0_BUS>;
+			clock-names = "core", "bus";
+			resets = <&syscon_apbc RESET_APBC_UART0>;
 			interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
@@ -461,7 +465,10 @@ uart2: serial@d4017100 {
 			reg = <0x0 0xd4017100 0x0 0x100>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clock-frequency = <14700000>;
+			clocks = <&syscon_apbc CLK_APBC_UART2>,
+				 <&syscon_apbc CLK_APBC_UART2_BUS>;
+			clock-names = "core", "bus";
+			resets = <&syscon_apbc RESET_APBC_UART2>;
 			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
@@ -471,7 +478,10 @@ uart3: serial@d4017200 {
 			reg = <0x0 0xd4017200 0x0 0x100>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clock-frequency = <14700000>;
+			clocks = <&syscon_apbc CLK_APBC_UART3>,
+				 <&syscon_apbc CLK_APBC_UART3_BUS>;
+			clock-names = "core", "bus";
+			resets = <&syscon_apbc RESET_APBC_UART3>;
 			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
@@ -481,7 +491,10 @@ uart4: serial@d4017300 {
 			reg = <0x0 0xd4017300 0x0 0x100>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clock-frequency = <14700000>;
+			clocks = <&syscon_apbc CLK_APBC_UART4>,
+				 <&syscon_apbc CLK_APBC_UART4_BUS>;
+			clock-names = "core", "bus";
+			resets = <&syscon_apbc RESET_APBC_UART4>;
 			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
@@ -491,7 +504,10 @@ uart5: serial@d4017400 {
 			reg = <0x0 0xd4017400 0x0 0x100>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clock-frequency = <14700000>;
+			clocks = <&syscon_apbc CLK_APBC_UART5>,
+				 <&syscon_apbc CLK_APBC_UART5_BUS>;
+			clock-names = "core", "bus";
+			resets = <&syscon_apbc RESET_APBC_UART5>;
 			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
@@ -501,7 +517,10 @@ uart6: serial@d4017500 {
 			reg = <0x0 0xd4017500 0x0 0x100>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clock-frequency = <14700000>;
+			clocks = <&syscon_apbc CLK_APBC_UART6>,
+				 <&syscon_apbc CLK_APBC_UART6_BUS>;
+			clock-names = "core", "bus";
+			resets = <&syscon_apbc RESET_APBC_UART6>;
 			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
@@ -511,7 +530,10 @@ uart7: serial@d4017600 {
 			reg = <0x0 0xd4017600 0x0 0x100>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clock-frequency = <14700000>;
+			clocks = <&syscon_apbc CLK_APBC_UART7>,
+				 <&syscon_apbc CLK_APBC_UART7_BUS>;
+			clock-names = "core", "bus";
+			resets = <&syscon_apbc RESET_APBC_UART7>;
 			interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
@@ -521,7 +543,10 @@ uart8: serial@d4017700 {
 			reg = <0x0 0xd4017700 0x0 0x100>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clock-frequency = <14700000>;
+			clocks = <&syscon_apbc CLK_APBC_UART8>,
+				 <&syscon_apbc CLK_APBC_UART8_BUS>;
+			clock-names = "core", "bus";
+			resets = <&syscon_apbc RESET_APBC_UART8>;
 			interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
@@ -531,7 +556,10 @@ uart9: serial@d4017800 {
 			reg = <0x0 0xd4017800 0x0 0x100>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clock-frequency = <14700000>;
+			clocks = <&syscon_apbc CLK_APBC_UART9>,
+				 <&syscon_apbc CLK_APBC_UART9_BUS>;
+			clock-names = "core", "bus";
+			resets = <&syscon_apbc RESET_APBC_UART9>;
 			interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
@@ -567,7 +595,10 @@ uart10: serial@d401f000 {
 			reg = <0x0 0xd401f000 0x0 0x100>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clock-frequency = <14700000>;
+			clocks = <&syscon_apbc CLK_APBC_UART10>,
+				 <&syscon_apbc CLK_APBC_UART10_BUS>;
+			clock-names = "core", "bus";
+			resets = <&syscon_apbc RESET_APBC_UART10>;
 			interrupts = <281 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};

-- 
2.53.0

Re: [PATCH 0/4] riscv: spacemit: k3: Add more resource to UART

[Yixun Lan]

On Wed, 04 Mar 2026 07:36:41 +0000, Yixun Lan wrote:
> This series try to add more resource (clock, pinctrl, reset) to UART driver,
> So it will not reply on external bootloader for initialization. While doing
> this, I've tried to break these patchse into more fine pieces, adding clock,
> pinctrl+gpio, reset separately, then UART.
> 
> 

Applied, thanks!

[1/4] riscv: dts: spacemit: k3: add clock tree
      https://github.com/spacemit-com/linux/commit/67072c8cd48c1fbb95cea39239eba5526395fcf5
[2/4] riscv: dts: spacemit: k3: add pinctrl support
      https://github.com/spacemit-com/linux/commit/d8944577496b5b99061d3b2020704fc86ab1f9e6
[3/4] riscv: dts: spacemit: k3: add GPIO support
      https://github.com/spacemit-com/linux/commit/20b77926864203e10b85af5276b17c2812d92ec1
[4/4] riscv: dts: spacemit: k3: add full resource to UART
      https://github.com/spacemit-com/linux/commit/28a7f755d7c9a4b9c41c12620fb4885f39b554ad

Best regards,
-- 
Yixun Lan <dlan@kernel.org>