[PATCH 0/3] usb: spacemit: k3: Add USB2.0 support

[PATCH 0/3] usb: spacemit: k3: Add USB2.0 support

[Yixun Lan]

There is one USB2.0 host in K3 SoC which actually use DWC3 IP but only 
provide USB2.0 functionality, and with only one USB2.0 PHY connected.

This series try to add USB2.0 support for SpacemiT K3 SoC, and also
enable it on Pico-ITX board. There is a run-time dependency on USB phy[1],
Hub[2] and reset[3] patches, but each series should be quite independent,
so I intend to not add prerequisite id for the dependency here.

For people who interested, I've collected all patches and put a complete
branch here[4].

Link: https://lore.kernel.org/r/20260305-11-k3-usb2-phy-v4-0-15554fb933bc@kernel.org [1]
Link: https://lore.kernel.org/r/20260317-03-usb-hub-fe1-v1-0-71ec3989f5be@kernel.org [2]
Link: https://lore.kernel.org/r/20260314-01-k3-reset-usb-pci-v2-1-9dc0976d524e@kernel.org [3]
Link: https://github.com/spacemit-com/linux/tree/WIP/k3/usb2 [4]
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
Yixun Lan (3):
      dt-bindings: usb: dwc3: spacemit: add support for K3 SoC
      usb: dwc3: dwc3-generic-plat: spacemit: add support for K3 SoC
      riscv: dts: spacemit: k3: Add USB2.0 support

 .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml  |  6 ++++-
 arch/riscv/boot/dts/spacemit/k3-pico-itx.dts       | 24 +++++++++++++++++
 arch/riscv/boot/dts/spacemit/k3.dtsi               | 31 ++++++++++++++++++++++
 drivers/usb/dwc3/dwc3-generic-plat.c               |  1 +
 4 files changed, 61 insertions(+), 1 deletion(-)
---
base-commit: c4c6e209dcf903ada6ddb4a0baca01ce8459a379
change-id: 20260312-02-k3-usb20-support-9a1893655e9d

Best regards,
-- 
Yixun Lan <dlan@kernel.org>

[PATCH 1/3] dt-bindings: usb: dwc3: spacemit: add support for K3 SoC

[Yixun Lan]

Add compatible string for DWC3 USB controller found in SpacemiT K3 SoC.
The USB2.0 host controller in K3 SoC actually use DWC3 IP but only has
USB2.0 functionality, and requires only one USB2.0 PHY connected.

Explicitly reduce number of phy property to minimal one.

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
 Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
index 0f0b5e061ca1..cc27b363ca79 100644
--- a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
@@ -27,7 +27,9 @@ allOf:
 
 properties:
   compatible:
-    const: spacemit,k1-dwc3
+    enum:
+      - spacemit,k1-dwc3
+      - spacemit,k3-dwc3
 
   reg:
     maxItems: 1
@@ -42,11 +44,13 @@ properties:
     maxItems: 1
 
   phys:
+    minItems: 1
     items:
       - description: phandle to USB2/HS PHY
       - description: phandle to USB3/SS PHY
 
   phy-names:
+    minItems: 1
     items:
       - const: usb2-phy
       - const: usb3-phy

-- 
2.53.0

[PATCH 2/3] usb: dwc3: dwc3-generic-plat: spacemit: add support for K3 SoC

[Yixun Lan]

Add support for the DWC3 USB controller which found in SpacemiT K3 SoC.

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
 drivers/usb/dwc3/dwc3-generic-plat.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
index e846844e0023..28219968b8b0 100644
--- a/drivers/usb/dwc3/dwc3-generic-plat.c
+++ b/drivers/usb/dwc3/dwc3-generic-plat.c
@@ -212,6 +212,7 @@ static const struct dwc3_generic_config eic7700_dwc3 =  {
 
 static const struct of_device_id dwc3_generic_of_match[] = {
 	{ .compatible = "spacemit,k1-dwc3", },
+	{ .compatible = "spacemit,k3-dwc3", },
 	{ .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3},
 	{ .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3},
 	{ /* sentinel */ }

-- 
2.53.0

[PATCH 3/3] riscv: dts: spacemit: k3: Add USB2.0 support

[Yixun Lan]

The USB2.0 controller on Pico-ITX board connnects to a Terminus FE1.1 Hub
which fully USB2.0 protocol compliant and provides 4 ports.

Signed-off-by: Yixun Lan <dlan@kernel.org>
---
 arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 24 +++++++++++++++++++++
 arch/riscv/boot/dts/spacemit/k3.dtsi         | 31 ++++++++++++++++++++++++++++
 2 files changed, 55 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
index b098dbd0e7a1..393a0ce65efc 100644
--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
@@ -23,6 +23,14 @@ memory@100000000 {
 		device_type = "memory";
 		reg = <0x1 0x00000000 0x4 0x00000000>;
 	};
+
+	aux_vcc3v3: regulator-aux-vcc3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "AUX_VCC3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
 };
 
 &uart0 {
@@ -30,3 +38,19 @@ &uart0 {
 	pinctrl-0 = <&uart0_0_cfg>;
 	status = "okay";
 };
+
+&usb2_host {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	hub@1 {
+		compatible = "usb1a40,0101";
+		reg = <1>;
+		vdd-supply = <&aux_vcc3v3>;
+	};
+};
+
+&usb2_phy {
+	status = "okay";
+};
diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index a3a8ceddabec..52be168a0496 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -438,6 +438,37 @@ soc: soc {
 		dma-noncoherent;
 		ranges;
 
+		usb2_host: usb@c0a00000 {
+			compatible = "spacemit,k3-dwc3";
+			reg = <0x0 0xc0a00000 0x0 0x10000>;
+			clocks = <&syscon_apmu CLK_APMU_USB2_BUS>;
+			clock-names = "usbdrd30";
+			resets = <&syscon_apmu RESET_APMU_USB2_AHB>,
+				 <&syscon_apmu RESET_APMU_USB2_VCC>,
+				 <&syscon_apmu RESET_APMU_USB2_PHY>;
+			reset-names = "ahb", "vcc", "phy";
+			interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&saplic>;
+			phys = <&usb2_phy>;
+			phy-names = "usb2-phy";
+			phy_type = "utmi";
+			snps,dis_enblslpm_quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			dr_mode = "host";
+			maximum-speed = "high-speed";
+			status = "disabled";
+		};
+
+		usb2_phy: phy@c0a20000 {
+			compatible = "spacemit,k3-usb2-phy";
+			reg = <0x0 0xc0a20000 0x0 0x200>;
+			clocks = <&syscon_apmu CLK_APMU_USB2_BUS>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
 		syscon_apbc: system-controller@d4015000 {
 			compatible = "spacemit,k3-syscon-apbc";
 			reg = <0x0 0xd4015000 0x0 0x1000>;

-- 
2.53.0

Re: [PATCH 1/3] dt-bindings: usb: dwc3: spacemit: add support for K3 SoC

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1479 bytes --]

On Tue, Mar 17, 2026 at 11:53:02AM +0000, Yixun Lan wrote:
> Add compatible string for DWC3 USB controller found in SpacemiT K3 SoC.
> The USB2.0 host controller in K3 SoC actually use DWC3 IP but only has
> USB2.0 functionality, and requires only one USB2.0 PHY connected.
> 
> Explicitly reduce number of phy property to minimal one.

Is this valid for the existing compatible, will it work with only one
clock?

> 
> Signed-off-by: Yixun Lan <dlan@kernel.org>
> ---
>  Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> index 0f0b5e061ca1..cc27b363ca79 100644
> --- a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> @@ -27,7 +27,9 @@ allOf:
>  
>  properties:
>    compatible:
> -    const: spacemit,k1-dwc3
> +    enum:
> +      - spacemit,k1-dwc3
> +      - spacemit,k3-dwc3
>  
>    reg:
>      maxItems: 1
> @@ -42,11 +44,13 @@ properties:
>      maxItems: 1
>  
>    phys:
> +    minItems: 1
>      items:
>        - description: phandle to USB2/HS PHY
>        - description: phandle to USB3/SS PHY
>  
>    phy-names:
> +    minItems: 1
>      items:
>        - const: usb2-phy
>        - const: usb3-phy
> 
> -- 
> 2.53.0
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 1/3] dt-bindings: usb: dwc3: spacemit: add support for K3 SoC

[Yixun Lan]

Hi Conor,

On 12:55 Tue 17 Mar     , Conor Dooley wrote:
> On Tue, Mar 17, 2026 at 11:53:02AM +0000, Yixun Lan wrote:
> > Add compatible string for DWC3 USB controller found in SpacemiT K3 SoC.
> > The USB2.0 host controller in K3 SoC actually use DWC3 IP but only has
> > USB2.0 functionality, and requires only one USB2.0 PHY connected.
> > 
> > Explicitly reduce number of phy property to minimal one.
> 
> Is this valid for the existing compatible, will it work with only one
> clock?
> 
I didn't change clock binding, do you mean phy?

Both k1 and k3 work with one clock (no change here)

for phy, the existing k1 requires two. for k3, one controller requires
one phy due to only has USB2.0 support, other controllers requires two
phys - USB2, USB3 PHY

> > 
> > Signed-off-by: Yixun Lan <dlan@kernel.org>
> > ---
> >  Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 6 +++++-
> >  1 file changed, 5 insertions(+), 1 deletion(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> > index 0f0b5e061ca1..cc27b363ca79 100644
> > --- a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> > +++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> > @@ -27,7 +27,9 @@ allOf:
> >  
> >  properties:
> >    compatible:
> > -    const: spacemit,k1-dwc3
> > +    enum:
> > +      - spacemit,k1-dwc3
> > +      - spacemit,k3-dwc3
> >  
> >    reg:
> >      maxItems: 1
> > @@ -42,11 +44,13 @@ properties:
> >      maxItems: 1
> >  
> >    phys:
> > +    minItems: 1
> >      items:
> >        - description: phandle to USB2/HS PHY
> >        - description: phandle to USB3/SS PHY
> >  
> >    phy-names:
> > +    minItems: 1
> >      items:
> >        - const: usb2-phy
> >        - const: usb3-phy
> > 
> > -- 
> > 2.53.0
> > 



-- 
Yixun Lan (dlan)

Re: [PATCH 2/3] usb: dwc3: dwc3-generic-plat: spacemit: add support for K3 SoC

[Thinh Nguyen]

On Tue, Mar 17, 2026, Yixun Lan wrote:
> Add support for the DWC3 USB controller which found in SpacemiT K3 SoC.
> 
> Signed-off-by: Yixun Lan <dlan@kernel.org>
> ---
>  drivers/usb/dwc3/dwc3-generic-plat.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
> index e846844e0023..28219968b8b0 100644
> --- a/drivers/usb/dwc3/dwc3-generic-plat.c
> +++ b/drivers/usb/dwc3/dwc3-generic-plat.c
> @@ -212,6 +212,7 @@ static const struct dwc3_generic_config eic7700_dwc3 =  {
>  
>  static const struct of_device_id dwc3_generic_of_match[] = {
>  	{ .compatible = "spacemit,k1-dwc3", },
> +	{ .compatible = "spacemit,k3-dwc3", },
>  	{ .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3},
>  	{ .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3},
>  	{ /* sentinel */ }
> 
> -- 
> 2.53.0
> 

Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>

BR,
Thinh

Re: [PATCH 3/3] riscv: dts: spacemit: k3: Add USB2.0 support

[Krzysztof Kozlowski]

On Tue, Mar 17, 2026 at 11:53:04AM +0000, Yixun Lan wrote:
> The USB2.0 controller on Pico-ITX board connnects to a Terminus FE1.1 Hub
> which fully USB2.0 protocol compliant and provides 4 ports.
> 
> Signed-off-by: Yixun Lan <dlan@kernel.org>
> ---
>  arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 24 +++++++++++++++++++++
>  arch/riscv/boot/dts/spacemit/k3.dtsi         | 31 ++++++++++++++++++++++++++++
>  2 files changed, 55 insertions(+)
> 

DTS cannot be combined in this patchset and must be split. Don't mix
patches from independent subsystems when you send something explicitly
targeting only one subsystem.
See also: Documentation/devicetree/bindings/submitting-patches.rst

Best regards,
Krzysztof

Re: [PATCH 1/3] dt-bindings: usb: dwc3: spacemit: add support for K3 SoC

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2317 bytes --]

On Wed, Mar 18, 2026 at 05:44:35AM +0800, Yixun Lan wrote:
> Hi Conor,
> 
> On 12:55 Tue 17 Mar     , Conor Dooley wrote:
> > On Tue, Mar 17, 2026 at 11:53:02AM +0000, Yixun Lan wrote:
> > > Add compatible string for DWC3 USB controller found in SpacemiT K3 SoC.
> > > The USB2.0 host controller in K3 SoC actually use DWC3 IP but only has
> > > USB2.0 functionality, and requires only one USB2.0 PHY connected.
> > > 
> > > Explicitly reduce number of phy property to minimal one.
> > 
> > Is this valid for the existing compatible, will it work with only one
> > clock?
> > 
> I didn't change clock binding, do you mean phy?
> 
> Both k1 and k3 work with one clock (no change here)
> 
> for phy, the existing k1 requires two. for k3, one controller requires
> one phy due to only has USB2.0 support, other controllers requires two
> phys - USB2, USB3 PHY

Yep, phy is what I meant. Sorry bout that. Since you're relaxing the
constraints for the k1, can you please add a conditional section to the
binding to enforce 2 phys min for k1?

> 
> > > 
> > > Signed-off-by: Yixun Lan <dlan@kernel.org>
> > > ---
> > >  Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 6 +++++-
> > >  1 file changed, 5 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> > > index 0f0b5e061ca1..cc27b363ca79 100644
> > > --- a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> > > +++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> > > @@ -27,7 +27,9 @@ allOf:
> > >  
> > >  properties:
> > >    compatible:
> > > -    const: spacemit,k1-dwc3
> > > +    enum:
> > > +      - spacemit,k1-dwc3
> > > +      - spacemit,k3-dwc3
> > >  
> > >    reg:
> > >      maxItems: 1
> > > @@ -42,11 +44,13 @@ properties:
> > >      maxItems: 1
> > >  
> > >    phys:
> > > +    minItems: 1
> > >      items:
> > >        - description: phandle to USB2/HS PHY
> > >        - description: phandle to USB3/SS PHY
> > >  
> > >    phy-names:
> > > +    minItems: 1
> > >      items:
> > >        - const: usb2-phy
> > >        - const: usb3-phy
> > > 
> > > -- 
> > > 2.53.0
> > > 
> 
> 
> 
> -- 
> Yixun Lan (dlan)

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 1/3] dt-bindings: usb: dwc3: spacemit: add support for K3 SoC

[Yixun Lan]

Hi Conor,

On 17:21 Wed 18 Mar     , Conor Dooley wrote:
> On Wed, Mar 18, 2026 at 05:44:35AM +0800, Yixun Lan wrote:
> > Hi Conor,
> > 
> > On 12:55 Tue 17 Mar     , Conor Dooley wrote:
> > > On Tue, Mar 17, 2026 at 11:53:02AM +0000, Yixun Lan wrote:
> > > > Add compatible string for DWC3 USB controller found in SpacemiT K3 SoC.
> > > > The USB2.0 host controller in K3 SoC actually use DWC3 IP but only has
> > > > USB2.0 functionality, and requires only one USB2.0 PHY connected.
> > > > 
> > > > Explicitly reduce number of phy property to minimal one.
> > > 
> > > Is this valid for the existing compatible, will it work with only one
> > > clock?
> > > 
> > I didn't change clock binding, do you mean phy?
> > 
> > Both k1 and k3 work with one clock (no change here)
> > 
> > for phy, the existing k1 requires two. for k3, one controller requires
> > one phy due to only has USB2.0 support, other controllers requires two
> > phys - USB2, USB3 PHY
> 
> Yep, phy is what I meant. Sorry bout that. Since you're relaxing the
> constraints for the k1, can you please add a conditional section to the
> binding to enforce 2 phys min for k1?
> 

To be explicit, the change should be applied to both K1 and K3, even in K1
use case, it's perfectly fine for designer to choose enabling USB2.0
only, and leave the comb phy to pcie contoller, so only one phy required

While revisiting the DT file, the phy related property should be moved
to board level, but this is another thing we should fix..

-- 
Yixun Lan (dlan)

Re: [PATCH 1/3] dt-bindings: usb: dwc3: spacemit: add support for K3 SoC

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1639 bytes --]

On Thu, Mar 19, 2026 at 10:41:24AM +0800, Yixun Lan wrote:
> Hi Conor,
> 
> On 17:21 Wed 18 Mar     , Conor Dooley wrote:
> > On Wed, Mar 18, 2026 at 05:44:35AM +0800, Yixun Lan wrote:
> > > Hi Conor,
> > > 
> > > On 12:55 Tue 17 Mar     , Conor Dooley wrote:
> > > > On Tue, Mar 17, 2026 at 11:53:02AM +0000, Yixun Lan wrote:
> > > > > Add compatible string for DWC3 USB controller found in SpacemiT K3 SoC.
> > > > > The USB2.0 host controller in K3 SoC actually use DWC3 IP but only has
> > > > > USB2.0 functionality, and requires only one USB2.0 PHY connected.
> > > > > 
> > > > > Explicitly reduce number of phy property to minimal one.
> > > > 
> > > > Is this valid for the existing compatible, will it work with only one
> > > > clock?
> > > > 
> > > I didn't change clock binding, do you mean phy?
> > > 
> > > Both k1 and k3 work with one clock (no change here)
> > > 
> > > for phy, the existing k1 requires two. for k3, one controller requires
> > > one phy due to only has USB2.0 support, other controllers requires two
> > > phys - USB2, USB3 PHY
> > 
> > Yep, phy is what I meant. Sorry bout that. Since you're relaxing the
> > constraints for the k1, can you please add a conditional section to the
> > binding to enforce 2 phys min for k1?
> > 
> 
> To be explicit, the change should be applied to both K1 and K3, even in K1
> use case, it's perfectly fine for designer to choose enabling USB2.0
> only, and leave the comb phy to pcie contoller, so only one phy required

In that case, can you be more clear in the commit message about why this
is also being done for the k1 please?

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 1/3] dt-bindings: usb: dwc3: spacemit: add support for K3 SoC

[Yixun Lan]

Hi Conor,

On 14:36 Thu 19 Mar     , Conor Dooley wrote:
> On Thu, Mar 19, 2026 at 10:41:24AM +0800, Yixun Lan wrote:
> > Hi Conor,
> > 
> > On 17:21 Wed 18 Mar     , Conor Dooley wrote:
> > > On Wed, Mar 18, 2026 at 05:44:35AM +0800, Yixun Lan wrote:
> > > > Hi Conor,
> > > > 
> > > > On 12:55 Tue 17 Mar     , Conor Dooley wrote:
> > > > > On Tue, Mar 17, 2026 at 11:53:02AM +0000, Yixun Lan wrote:
> > > > > > Add compatible string for DWC3 USB controller found in SpacemiT K3 SoC.
> > > > > > The USB2.0 host controller in K3 SoC actually use DWC3 IP but only has
> > > > > > USB2.0 functionality, and requires only one USB2.0 PHY connected.
> > > > > > 
> > > > > > Explicitly reduce number of phy property to minimal one.
> > > > > 
> > > > > Is this valid for the existing compatible, will it work with only one
> > > > > clock?
> > > > > 
> > > > I didn't change clock binding, do you mean phy?
> > > > 
> > > > Both k1 and k3 work with one clock (no change here)
> > > > 
> > > > for phy, the existing k1 requires two. for k3, one controller requires
> > > > one phy due to only has USB2.0 support, other controllers requires two
> > > > phys - USB2, USB3 PHY
> > > 
> > > Yep, phy is what I meant. Sorry bout that. Since you're relaxing the
> > > constraints for the k1, can you please add a conditional section to the
> > > binding to enforce 2 phys min for k1?
> > > 
> > 
> > To be explicit, the change should be applied to both K1 and K3, even in K1
> > use case, it's perfectly fine for designer to choose enabling USB2.0
> > only, and leave the comb phy to pcie contoller, so only one phy required
> 
> In that case, can you be more clear in the commit message about why this
> is also being done for the k1 please?

sure, I will do it in v2

-- 
Yixun Lan (dlan)