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From: Yixun Lan <dlan@kernel.org>
To: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Cc: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	spacemit@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] riscv: dts: spacemit: Add PDMA controller node for K3 SoC
Date: Fri, 20 Mar 2026 17:19:36 +0800	[thread overview]
Message-ID: <20260320091936-GKB525649@kernel.org> (raw)
In-Reply-To: <20260317-k3-pdma-v1-1-f39d3e97b53a@linux.spacemit.com>

Hi Troy,

On 15:55 Tue 17 Mar     , Troy Mitchell wrote:
> Add the Peripheral DMA (PDMA) controller node for the SpacemiT K3 SoC.
> The PDMA controller provides general-purpose DMA capabilities for various
> peripheral devices across the system to offload CPU data transfers.
> 
> Unlike the previous K1 SoC, where some DMA masters had memory addressing
> limitations (e.g. restricted to the 0-4GB space) requiring a dedicated dma-bus
> with dma-ranges to restrict memory allocations, the K3 DMA masters have
> full memory addressing capabilities. Therefore, the PDMA node is now
> instantiated directly under the main soc bus.
> 
..
> This configuration defines the essential hardware properties:
> - Register base address and size
> - High-level triggered interrupt
> - Associated APMU clock and reset controls
> - 16 hardware DMA channels
> 
> The node is disabled by default and should be enabled by specific
> board device trees as needed.
I would suggest to drop above, as they are quite obvious, and easy for 
people to grab from the code..
> 
> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
> ---
>  arch/riscv/boot/dts/spacemit/k3.dtsi | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> index a3a8ceddabec..f90d34a81be0 100644
> --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> @@ -438,6 +438,17 @@ soc: soc {
>  		dma-noncoherent;
>  		ranges;
>  
> +		pdma: dma-controller@d4000000 {
> +			compatible = "spacemit,k1-pdma";
I think here we should introduce a new compatible for K3 SoC,
it would avoid ABI breakage if something different with K1?
cases exist even same PDMA IP integrated into different SoC..

The commit message tells some difference, although no code changes
introduced so far..

> +			reg = <0x0 0xd4000000 0x0 0x4000>;
> +			clocks = <&syscon_apmu CLK_APMU_DMA>;
> +			resets = <&syscon_apmu RESET_APMU_DMA>;
> +			interrupts = <72 IRQ_TYPE_LEVEL_HIGH>;
> +			dma-channels = <16>;
> +			#dma-cells = <1>;
> +			status = "disabled";
> +		};
> +
>  		syscon_apbc: system-controller@d4015000 {
>  			compatible = "spacemit,k3-syscon-apbc";
>  			reg = <0x0 0xd4015000 0x0 0x1000>;
> 
> ---
> base-commit: 95c541ddfb0815a0ea8477af778bb13bb075079a
> change-id: 20260317-k3-pdma-7c1734431436
> 
> Best regards,
> -- 
> Troy Mitchell <troy.mitchell@linux.spacemit.com>
> 

-- 
Yixun Lan (dlan)

  reply	other threads:[~2026-03-20  9:19 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-17  7:55 [PATCH] riscv: dts: spacemit: Add PDMA controller node for K3 SoC Troy Mitchell
2026-03-20  9:19 ` Yixun Lan [this message]
2026-03-24  8:43   ` Troy Mitchell

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