From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A7A537646E for ; Fri, 20 Mar 2026 10:09:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=90.155.92.199 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774001355; cv=none; b=tluDX5srGmxfyYNBmi5Wvc+QfZGHEkNlhKBf5VFnfjPLYfGDmCc8Zrd57XxNko9QPLK3oDeUiYhsonh9ZSjeUwlGQvecPfwMUGdVW0aQNkMe7WFDQH2tuH63UwBt7+9LsYv4URs7wFE3uq2MwadUwIu9l5pY7gsHCET9FmHyMGg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774001355; c=relaxed/simple; bh=r+V4IEzxiSBRD+PEQ0bcS3T+ceWMATpscsfSkV/7MyQ=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=rJwEJLW7GpZOobzqmx0iGG6hjuA24BhXjLFASuoWS0w0XD7zGB38YjTrH98x6sltMfqTrT+9DyTTuxDz4OTsvKblOfuy1dYShbaU8DmhoHmRKNC552VsvfDYcNiqs23bOqiB4R9gujvD0k4FVB2oXTgs4VMoKwg47Ygxnio3FH0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=infradead.org; spf=none smtp.mailfrom=infradead.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b=SdR/UaIN; arc=none smtp.client-ip=90.155.92.199 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=infradead.org Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=infradead.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="SdR/UaIN" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=zOa3mBpfLtnhZpSpM5yPa44FY3d9TGxu6bHqLrkWZ+0=; b=SdR/UaINHsody3oQe4Wk1ehDVV BWFngk24wSa0VtKc3KbAjPzcb5sB7V/v6MAHM9Em9qj8Zw1+XuGh9A6WfJDlu2HXJdhxXXQWzsX0B Z0bv5NorWUbLCaVCuRZZoNstyuYnwbGtwhX4VuWDMp8mPRI0D+rexzvlYgSeHaGuLV4ZLd757+K4/ Ka4esBjzqaw2/7R3j1R6ZU9tc5gWR6LuQe5TsKgP5vkNgiZolxvgTdZ2PSv6fm9fZy1o8a/xn7WLQ nVRGJmoP8skjM53vxfvRRJn5zZcpys4CTZ0Fme14FIcFEniF4/eOxujLMBtEuJfnIk5j61Ycnb6Ju pxvpXNIQ==; Received: from 2001-1c00-8d85-5700-266e-96ff-fe07-7dcc.cable.dynamic.v6.ziggo.nl ([2001:1c00:8d85:5700:266e:96ff:fe07:7dcc] helo=noisy.programming.kicks-ass.net) by desiato.infradead.org with esmtpsa (Exim 4.98.2 #2 (Red Hat Linux)) id 1w3Wn0-0000000FIPB-0Zj7; Fri, 20 Mar 2026 10:09:10 +0000 Received: by noisy.programming.kicks-ass.net (Postfix, from userid 1000) id 137C6301150; Fri, 20 Mar 2026 11:09:03 +0100 (CET) Date: Fri, 20 Mar 2026 11:09:03 +0100 From: Peter Zijlstra To: Pan Deng Cc: mingo@kernel.org, linux-kernel@vger.kernel.org, tianyou.li@intel.com, tim.c.chen@linux.intel.com, yu.c.chen@intel.com Subject: Re: [PATCH v2 1/4] sched/rt: Optimize cpupri_vec layout to mitigate cache line contention Message-ID: <20260320100903.GR3738786@noisy.programming.kicks-ass.net> References: <24c460fb48d86a5b990acbb42d0d29d91dfc427c.1753076363.git.pan.deng@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <24c460fb48d86a5b990acbb42d0d29d91dfc427c.1753076363.git.pan.deng@intel.com> On Mon, Jul 21, 2025 at 02:10:23PM +0800, Pan Deng wrote: > When running a multi-instance FFmpeg workload on an HCC system, significant > cache line contention is observed around `cpupri_vec->count` and `mask` in > struct root_domain. > > The SUT is a 2-socket machine with 240 physical cores and 480 logical > CPUs. 60 FFmpeg instances are launched, each pinned to 4 physical cores > (8 logical CPUs) for transcoding tasks. Sub-threads use RT priority 99 > with FIFO scheduling. FPS is used as score. > > perf c2c tool reveals: > root_domain cache line 3: > - `cpupri->pri_to_cpu[0].count` (offset 0x38) is heavily loaded/stored > and contends with other fields, since counts[0] is more frequently > updated than others along with a rt task enqueues an empty runq or > dequeues from a non-overloaded runq. > - cycles per load: ~10K to 59K > > cpupri's last cache line: > - `cpupri_vec->count` and `mask` contends. The transcoding threads use > rt pri 99, so that the contention occurs in the end. > - cycles per load: ~1.5K to 10.5K > > This change mitigates `cpupri_vec->count`, `mask` related contentions by > separating each count and mask into different cache lines. Right. > Note: The side effect of this change is that struct cpupri size is > increased from 26 cache lines to 203 cache lines. That is pretty horrible, but probably unavoidable. > An alternative implementation of this patch could be separating `counts` > and `masks` into 2 vectors in cpupri_vec (counts[] and masks[]), and > add two paddings: > 1. Between counts[0] and counts[1], since counts[0] is more frequently > updated than others. That is completely workload specific; it is a direct consequence of your (probably busted) priority assignment scheme. > 2. Between the two vectors, since counts[] is read-write access while > masks[] is read access when it stores pointers. > > The alternative introduces the complexity of 31+/21- LoC changes, > it achieves almost the same performance, at the same time, struct cpupri > size is reduced from 26 cache lines to 21 cache lines. That is not an alternative, since it very specifically only deals with fifo-99 contention. > --- > kernel/sched/cpupri.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/kernel/sched/cpupri.h b/kernel/sched/cpupri.h > index d6cba0020064..245b0fa626be 100644 > --- a/kernel/sched/cpupri.h > +++ b/kernel/sched/cpupri.h > @@ -9,7 +9,7 @@ > > struct cpupri_vec { > atomic_t count; > - cpumask_var_t mask; > + cpumask_var_t mask ____cacheline_aligned; > }; At the very least this needs a comment, explaining the what and how of it.