From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F19F372ED9 for ; Fri, 20 Mar 2026 13:04:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=90.155.92.199 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774011882; cv=none; b=WKCo0TUIxOlrVeM/zfBMleDZXDVGSau4HTYtx+DKHDuSDjxAsT3GG9VA5Fq8eDLZXuGLrJlMEts4o7ymuaGKkHE0iVATOMBuBm8DDwhadcuGMlBYn5mzQtVfPjs+8hlwVs8dMIPHHtiFtR8uFQEQNXX0VjIInOg598IQRKTSLm0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774011882; c=relaxed/simple; bh=lF2Q2z9mhgUNieWdAgsspnMHqlCBgn/b/FVaMVv2n6c=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=R4z+4sDa4SfYh79l64YBIbwvHz6ZpSIA/CJQaenctW05SPIDvnk1qOzfGkhz6kK4xkPsuoRmoyCgLLV679E/DuFMn2r9vuG6EK7SRaLOg7kK/WVlY4/AcXZ5HTavhFucWK5Wx1P6n26hLuBIEF3vq9LugUmDzAYox/QnnEcaxQU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=infradead.org; spf=none smtp.mailfrom=infradead.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b=SvyBwp5A; arc=none smtp.client-ip=90.155.92.199 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=infradead.org Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=infradead.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="SvyBwp5A" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=fLLFjsvRlpzhP+3Wz85TDLwtJtc8fpi1Gf2qGKkrHqs=; b=SvyBwp5ApwHiEK8M0YI3p19AUM zphXuCAn1AoMIGi1mV0g2H3OTWbWx+bo2el6YPv60Zns2J5GeeQcF0/3nTcjmhS+ddus99B+HNF72 snVp8nqsN6yTiK4gz7I74Z2XKLHqKumX/pAWEDBfYnuDBKiwa86hrKfy1c/yIs39PojKnNxifW5Xz n+45VOys0vR92zfE0ZW+BQvtWAFkOOaj4Khx+kqbFo7+R41/My7JFhsbCc+RsiYaC8NHeaFpyARdP PehOnfNDPsLjKVtWdK3bvOUQVkhvAvyPkhCulN20yNvVKuBy5p2NiP8modfC3yEAlsBq8273DHk94 I+6jpzZg==; Received: from 77-249-17-252.cable.dynamic.v4.ziggo.nl ([77.249.17.252] helo=noisy.programming.kicks-ass.net) by desiato.infradead.org with esmtpsa (Exim 4.98.2 #2 (Red Hat Linux)) id 1w3ZWl-0000000FZwe-1OqY; Fri, 20 Mar 2026 13:04:35 +0000 Received: by noisy.programming.kicks-ass.net (Postfix, from userid 1000) id 587203004F8; Fri, 20 Mar 2026 14:04:33 +0100 (CET) Date: Fri, 20 Mar 2026 14:04:33 +0100 From: Peter Zijlstra To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, ada.coupriediaz@arm.com, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, luto@kernel.org, ruanjinjie@huawei.com, tglx@kernel.org, vladimir.murzin@arm.com, will@kernel.org Subject: Re: [PATCH 1/2] arm64/entry: Fix involuntary preemption exception masking Message-ID: <20260320130433.GV3738786@noisy.programming.kicks-ass.net> References: <20260320113026.3219620-1-mark.rutland@arm.com> <20260320113026.3219620-2-mark.rutland@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260320113026.3219620-2-mark.rutland@arm.com> On Fri, Mar 20, 2026 at 11:30:25AM +0000, Mark Rutland wrote: > Thomas, Peter, I have a couple of things I'd like to check: > > (1) The generic irq entry code will preempt from any exception (e.g. a > synchronous fault) where interrupts were unmasked in the original > context. Is that intentional/necessary, or was that just the way the > x86 code happened to be implemented? > > I assume that it'd be fine if arm64 only preempted from true > interrupts, but if that was intentional/necessary I can go rework > this. So NMI-from-kernel must not trigger resched IIRC. There is some code that relies on this somewhere. And on x86 many of those synchronous exceptions are marked as NMI, since they can happen with IRQs disabled inside locks etc. But for the rest I don't think we care particularly. Notably page-fault will already schedule itself when possible (faults leading to IO and blocking). > (2) The generic irq entry code only preempts when RCU was watching in > the original context. IIUC that's just to avoid preempting from the > idle thread. Is it functionally necessary to avoid that, or is that > just an optimization? > > I'm asking because historically arm64 didn't check that, and I > haven't bothered checking here. I don't know whether we have a > latent functional bug. Like I told you on IRC, I *think* this is just an optimization, since if you hit idle, the idle loop will take care of scheduling. But I can't quite remember the details here, and wish we'd have written a sensible comment at that spot. Other places where RCU isn't watching are userspace and KVM. The first isn't relevant because this is return-to-kernel, and the second I'm not sure about. Thomas, can you remember?