From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90B023BB9E4 for ; Fri, 20 Mar 2026 13:22:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774012943; cv=none; b=HTvN0gfPPPR37Ba5QlGe9efe9w4bMmCjcxclFJG+T2Y/6S22+Iymn43k23C9ImUmyFPyCkx0+mNerDbEvDD+d625XO2tNxBmwhXyuva+NmzndCyt/QTyNJffY0bCG1AsFrk2vJ2SkuDhp1yLQKyRAA7cx69Vaexdz5pPlEuGMtU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774012943; c=relaxed/simple; bh=LZ5V5KnNkhK0zSCP/yI0pLrdMCYdhpN1lNNhrspEuHc=; h=Date:Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type; b=lLS1819fsAuOLmpLuoL+8+VEY8fgXxUhW8Tx4hRqxAsMfY/kfRrjrMFjFdg/WqNxSm4txZwrNl2sBw4/M2l0rKdMy5JAUXbZIpvcjP2h5yptaJdTlBiRFMciBACXa484iLi4jC5T12/hk7AOGWnepQKUSLGCxoaMZ8VvDXAYdzw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LLhouzTv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LLhouzTv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9ADCFC4CEF7; Fri, 20 Mar 2026 13:22:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774012943; bh=LZ5V5KnNkhK0zSCP/yI0pLrdMCYdhpN1lNNhrspEuHc=; h=Date:From:To:Cc:Subject:References:From; b=LLhouzTvOCDfHTpCQ47QXCtu34mrT8BfIvVHOaIxbPHAxxB/ahtoyjN1hy5Lou1q9 lJ+7eqBzka5XoyMbYJKFZ33ps9PxHJRM+M5H4dy0qMxeBGtpACXCZbiStYCx17dk5f T+yTOnTyrW3djmgp6Tp8khgUYip1xjua+kwqPKCroS5a6DIHXPDPp8zNiK/VGbQidd /eYCUhOgFKrxY7o9Bar9CqdalyMJfw3Av5hjoqJo4uTp2xAKntLqjj8BGQfosH6DXD kh4H8+JdpIjOV8HxwcxNuYGsXvgPq9Ed9u89X4whhUVRogHn9YkhCqEq48prAAVYku oM8yUF7jvU2mw== Date: Fri, 20 Mar 2026 14:22:19 +0100 Message-ID: <20260320132102.774348989@kernel.org> User-Agent: quilt/0.68 From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Dmitry Ilvokhin , Neil Horman , Radu Rendec Subject: [patch v2 11/14] [RFC] genirq: Cache target CPU for single CPU affinities References: <20260320131108.344376329@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Some places can be optimized by caching the target CPU for single CPU affinities. That avoids finding the single CPU in the effective affinity mask. Provide infrastructure for that. Signed-off-by: Thomas Gleixner --- include/linux/irq.h | 17 +++++++++++++++++ kernel/irq/manage.c | 14 ++++++++++---- 2 files changed, 27 insertions(+), 4 deletions(-) --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -140,6 +140,8 @@ struct irq_domain; * @effective_affinity: The effective IRQ affinity on SMP as some irq * chips do not allow multi CPU destinations. * A subset of @affinity. + * @target_cpu: The target CPU when @effective_affinity contains + * only a single CPU, IRQ_TARGET_MULTI_CPU otherwise * @msi_desc: MSI descriptor * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional. */ @@ -155,6 +157,7 @@ struct irq_common_data { #endif #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK cpumask_var_t effective_affinity; + unsigned int target_cpu; #endif #ifdef CONFIG_GENERIC_IRQ_IPI unsigned int ipi_offset; @@ -903,6 +906,8 @@ static inline const struct cpumask *irq_ return d ? irq_data_get_affinity_mask(d) : NULL; } +#define IRQ_TARGET_MULTI_CPU UINT_MAX + #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK static inline const struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) @@ -914,6 +919,14 @@ static inline void irq_data_update_effec { cpumask_copy(d->common->effective_affinity, m); } +static inline unsigned int irq_data_get_single_target(struct irq_data *d) +{ + return d->common->target_cpu; +} +static inline void irq_data_set_single_target(struct irq_data *d, unsigned int cpu) +{ + d->common->target_cpu = cpu; +} #else static inline void irq_data_update_effective_affinity(struct irq_data *d, const struct cpumask *m) @@ -924,6 +937,10 @@ const struct cpumask *irq_data_get_effec { return irq_data_get_affinity_mask(d); } +static inline unsigned int irq_data_get_single_target(struct irq_data *d) +{ + return IRQ_TARGET_MULTI_CPU; +} #endif static inline --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -217,11 +217,17 @@ static void irq_validate_effective_affin { const struct cpumask *m = irq_data_get_effective_affinity_mask(data); struct irq_chip *chip = irq_data_get_irq_chip(data); + unsigned int target = IRQ_TARGET_MULTI_CPU; - if (!cpumask_empty(m)) - return; - pr_warn_once("irq_chip %s did not update eff. affinity mask of irq %u\n", - chip->name, data->irq); + switch (cpumask_weight(m)) { + case 0: + pr_warn_once("irq_chip %s did not update eff. affinity mask of irq %u\n", + chip->name, data->irq); + break; + case 1: + target = cpumask_first(m); + } + irq_data_set_single_target(data, target); } #else static inline void irq_validate_effective_affinity(struct irq_data *data) { }