From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11A683D902F for ; Tue, 24 Mar 2026 09:00:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.206.16.166 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774342834; cv=none; b=aJVO6sEucbbYUFvnjQtDc04D39/7Cdioqc7QGuPCoQYPV/wVdWWJHBwWQKIZZ9yOhV6bEkZhHwmbGLhVGqNf0F4H0xw9j120dM3D/l2CozApwyQRtZeFU6Hmj6CiySwvAr2D7yo+aWq4UKuFSwxIJPQzExFBZkO85xhIwi/cnYE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774342834; c=relaxed/simple; bh=GPh/tb/DQXFJNFVadMYGg2u6+Pvy1hCnu2qEN5EoHoQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=jI7jXYhPldYQcVnHG3Ul4FVGCmI8V7Utcn4wgTjib2Zb/Nl5N9bv0NoAp2jzOF4rrlxFBZ8b2wk4jqtCapjHlElTPa+ZAasAPIErTA6/NYQ0Df+yQVT+N0LgZFZdhE91DaM4f3wAQ93zbg9pEoNziQf8kOynExLn4EiC0FpVBcI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=airkyi.com; spf=pass smtp.mailfrom=airkyi.com; dkim=pass (1024-bit key) header.d=airkyi.com header.i=@airkyi.com header.b=l4SdTo8P; arc=none smtp.client-ip=54.206.16.166 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=airkyi.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=airkyi.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=airkyi.com header.i=@airkyi.com header.b="l4SdTo8P" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=airkyi.com; s=altu2504; t=1774342729; bh=vm1hlDqmKXhzeCh+KQFR50RFAmb9kKA0Is7jJbuWqoI=; h=From:To:Subject:Date:Message-Id; b=l4SdTo8PGbJnc6wP0X8BoxgcQg1pghujp5+RHJZSJFnjL+jYycagoEsyuyAqTZAIK 6F4h8g2ZsNXYA+UU96jaBOLY4q+IH92dPUm5NdhVAIUbgNbmVY7YgFyQK1Qs7lNDbF mEWIgZD3L0KjMIOkR/Fk9HfyIx68JgNivsNuovdY= X-QQ-mid: zesmtpsz6t1774342727ta21bc527 X-QQ-Originating-IP: IHv6lcjJAJuvhmLwDjGDc7WZxEnZ7E43PSgpt7vO96E= Received: from DESKTOP-8BT1A2O.localdomain ( [58.22.7.114]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 24 Mar 2026 16:58:44 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 70989701443184399 From: Chaoyi Chen To: Sandy Huang , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Guochun Huang Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Chaoyi Chen Subject: [PATCH 2/2] drm/rockchip: dsi: Add dphy_get_timing support for multiple PHY types Date: Tue, 24 Mar 2026 16:58:38 +0800 Message-Id: <20260324085838.90-2-kernel@airkyi.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260324085838.90-1-kernel@airkyi.com> References: <20260324085838.90-1-kernel@airkyi.com> X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpsz:airkyi.com:qybglogicsvrgz:qybglogicsvrgz6b-0 X-QQ-XMAILINFO: NvH2zBBgt3uTYlBkO4TEuFs6TFUkwdFz3x09l/ZRSJRUimUavU7YgWWw jretf57eQTQbEO5k1i7NRbXW0AupIvN+Kat+AB1+BtcT+wdiT8FF37O38RYgtQDr+MsgWgx Jd+NAwKbDQjVU2q0wYkaj6FcNI7+I2eCrbQo7TvpLd37Z5fFKXXfhobsg7fVDgx4gi/4BMQ o3n81gSIODq1JhXKAXuGw2KreRlDRkC9V+IvJch5/yh0bgIgCl1McgANkUfsIYG1UbORrlj foB7VM4zrohXssHsTNG3zyyb6vRHrIJhv9CR+q7ditvHHfE9ftCdIJogAUXrlh1aNJLQmWq pqrPWeaAfMb1CGHGvOeWX/t8Ucw/FB5pBR6zU8PogVvRWC+c01SZaICQGzkL/uGBbaBEAX0 kE/DoqdA3dmcCAtCJ6kR68EhbRMmsiliGRmoCnZloLrJ6Cx0AO2zkwLPeotNWdzzhPvUUu/ uGnEjIZj3SmHTOEjGzesK2cB6kvAlpTd4c050Huxwzv6/2CDN4GvDpRqEuVc9s0SbG/P3du 2t8YuVZ2XZVgabdDUU75vEGveP9B/g2+SxBR6RWW+yW1H/f0OCEARPOMDgkG58Olrr4VkUj 570TB7a8uPZWO4i7lIHvVr2+2skb6edh/0BPwasG/nGy/jpstT192QuLeEk1X9QC9zCc+Lv 9MZpWQ/xavo7y2HNq9gcEJOABcDIKg9eZ7QoO79F49IgVy0x9eahSs7Ypgi7sKhVMzyzr0M PF7GC53oSgQ8yKOELYvJY28ZjUxIkUkYEktGPMnZIL5J0HCj3kEcaYYKgcmJdl0Bn0GPfdY uVredV9xq1VflUGzfxuqgXhT+fd+FRCV+pWInobIFVR7JFB9JwkXXmeyte4yeQrXfBdcGHS zBXqqDIh7aCxBOhWsTME++DTTcj77nkbHtrYl/YdLY6VDnGj2xZYm0ZQWK/tcNbgD2nY8Wi XVRMbaM4JTGKI80RrmER84zN65fHvYck0FWdK8GgFgWEeD4JZCesRhaNPvniFln0jFvHzeS x5J6xOATKkXCfl9UZu X-QQ-XMRINFO: Nq+8W0+stu50tPAe92KXseR0ZZmBTk3gLg== X-QQ-RECHKSPAM: 0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: From: Chaoyi Chen Currently, there are generally two types of DPHY for Rockchip. One is the DPHY used by RK3288/RK3399, whose timing is described by Table A-3 High-Speed Transition Times in the databook. The other is the DPHY used by PX30 and its successors. If its timing is still described using RK3288/RK3399, it may not perform correctly on some DSI panel. Add dphy_get_timing for different D-PHY types to adapt to timing differences. Signed-off-by: Chaoyi Chen --- .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 45 ++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index d3bacfae174e..2d1c9e54ff85 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -247,6 +247,7 @@ enum { BIASEXTR_127_7, }; +struct dw_mipi_dsi_rockchip; struct rockchip_dw_dsi_chip_data { u32 reg; @@ -262,6 +263,9 @@ struct rockchip_dw_dsi_chip_data { u32 lanecfg2_grf_reg; u32 lanecfg2; + int (*dphy_get_timing)(struct dw_mipi_dsi_rockchip *dsi, unsigned int lane_mbps, + struct dw_mipi_dsi_dphy_timing *timing); + int (*dphy_rx_init)(struct phy *phy); int (*dphy_rx_power_on)(struct phy *phy); int (*dphy_rx_power_off)(struct phy *phy); @@ -721,8 +725,9 @@ static struct hstt hstt_table[] = { }; static int -dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, - struct dw_mipi_dsi_dphy_timing *timing) +dw_mipi_dsi_phy_rk3288_get_timing(struct dw_mipi_dsi_rockchip *dsi, + unsigned int lane_mbps, + struct dw_mipi_dsi_dphy_timing *timing) { int i; @@ -738,6 +743,32 @@ dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, return 0; } +static const struct dw_mipi_dsi_dphy_timing dphy_timing_px30 = { + .clk_lp2hs = 0x40, + .clk_hs2lp = 0x40, + .data_lp2hs = 0x10, + .data_hs2lp = 0x14, +}; + +static int +dw_mipi_dsi_phy_px30_get_timing(struct dw_mipi_dsi_rockchip *dsi, + unsigned int lane_mbps, + struct dw_mipi_dsi_dphy_timing *timing) +{ + *timing = dphy_timing_px30; + + return 0; +} + +static int +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, + struct dw_mipi_dsi_dphy_timing *timing) +{ + struct dw_mipi_dsi_rockchip *dsi = priv_data; + + return dsi->cdata->dphy_get_timing(dsi, lane_mbps, timing); +} + static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = { .init = dw_mipi_dsi_phy_init, .power_on = dw_mipi_dsi_phy_power_on, @@ -1506,6 +1537,7 @@ static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = { .max_data_lanes = 4, .max_bit_rate_per_lane = 1000000000UL, + .dphy_get_timing = dw_mipi_dsi_phy_px30_get_timing, }, { /* sentinel */ } }; @@ -1519,6 +1551,7 @@ static const struct rockchip_dw_dsi_chip_data rk3128_chip_data[] = { RK3128_DSI_FORCETXSTOPMODE), 0), .max_data_lanes = 4, .max_bit_rate_per_lane = 1000000000UL, + .dphy_get_timing = dw_mipi_dsi_phy_px30_get_timing, }, { /* sentinel */ } }; @@ -1532,6 +1565,7 @@ static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { .max_data_lanes = 4, .max_bit_rate_per_lane = 1500000000UL, + .dphy_get_timing = dw_mipi_dsi_phy_rk3288_get_timing, }, { .reg = 0xff964000, @@ -1541,6 +1575,7 @@ static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { .max_data_lanes = 4, .max_bit_rate_per_lane = 1500000000UL, + .dphy_get_timing = dw_mipi_dsi_phy_rk3288_get_timing, }, { /* sentinel */ } }; @@ -1554,6 +1589,7 @@ static const struct rockchip_dw_dsi_chip_data rk3368_chip_data[] = { RK3368_DSI_FORCERXMODE), 0), .max_data_lanes = 4, .max_bit_rate_per_lane = 1500000000UL, + .dphy_get_timing = dw_mipi_dsi_phy_px30_get_timing, }, { /* sentinel */ } }; @@ -1642,6 +1678,7 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, .max_data_lanes = 4, .max_bit_rate_per_lane = 1500000000UL, + .dphy_get_timing = dw_mipi_dsi_phy_rk3288_get_timing, }, { .reg = 0xff968000, @@ -1671,6 +1708,7 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { .dphy_rx_init = rk3399_dphy_tx1rx1_init, .dphy_rx_power_on = rk3399_dphy_tx1rx1_power_on, .dphy_rx_power_off = rk3399_dphy_tx1rx1_power_off, + .dphy_get_timing = dw_mipi_dsi_phy_rk3288_get_timing, }, { /* sentinel */ } }; @@ -1698,6 +1736,7 @@ static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCERXMODE, 0)), .max_data_lanes = 4, .max_bit_rate_per_lane = 1200000000UL, + .dphy_get_timing = dw_mipi_dsi_phy_px30_get_timing, }, { .reg = 0xfe070000, @@ -1708,6 +1747,7 @@ static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCERXMODE, 0)), .max_data_lanes = 4, .max_bit_rate_per_lane = 1200000000UL, + .dphy_get_timing = dw_mipi_dsi_phy_px30_get_timing, }, { /* sentinel */ } }; @@ -1721,6 +1761,7 @@ static const struct rockchip_dw_dsi_chip_data rv1126_chip_data[] = { FIELD_PREP_WM16_CONST(RV1126_DSI_FORCETXSTOPMODE, 0)), .max_data_lanes = 4, .max_bit_rate_per_lane = 1000000000UL, + .dphy_get_timing = dw_mipi_dsi_phy_px30_get_timing, }, { /* sentinel */ } }; -- 2.51.1