From: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com
Cc: platform-driver-x86@vger.kernel.org,
linux-kernel@vger.kernel.org,
Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Subject: [PATCH] platform/x86/intel/tpmi: Use 32 bit aligned address for debugfs mem write
Date: Wed, 25 Mar 2026 12:30:48 -0700 [thread overview]
Message-ID: <20260325193048.3417349-1-srinivas.pandruvada@linux.intel.com> (raw)
The memory write feature supports 32-bit writes to any TPMI offset.
However, future hardware generations may not allow writes to non-32-bit
aligned addresses due to hardware optimizations.
Since all TPMI addresses are 64-bit aligned and correspond to 64-bit
registers, enforce 32-bit alignment for write operations.
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
---
drivers/platform/x86/intel/vsec_tpmi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/platform/x86/intel/vsec_tpmi.c b/drivers/platform/x86/intel/vsec_tpmi.c
index 98846e88d3d0..b70232d8ba58 100644
--- a/drivers/platform/x86/intel/vsec_tpmi.c
+++ b/drivers/platform/x86/intel/vsec_tpmi.c
@@ -479,6 +479,9 @@ static ssize_t mem_write(struct file *file, const char __user *userbuf, size_t l
addr = array[2];
value = array[3];
+ if (addr % sizeof(u32))
+ return -EINVAL;
+
if (punit >= pfs->pfs_header.num_entries) {
ret = -EINVAL;
goto exit_write;
--
2.52.0
next reply other threads:[~2026-03-25 19:30 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-25 19:30 Srinivas Pandruvada [this message]
2026-03-26 10:28 ` [PATCH] platform/x86/intel/tpmi: Use 32 bit aligned address for debugfs mem write Ilpo Järvinen
2026-03-26 15:13 ` srinivas pandruvada
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