Re: [PATCH v3] PCI: pciehp: Fix hotplug on Catlow Lake with unreliable PME status

Lukas Wunner
2026-03-23T12:53:40Z

On Mon, Mar 16, 2026 at 03:08:06PM -0700, Kuppuswamy Sathyanarayanan wrote:
> On Intel Catlow Lake platforms, PCH PCIe root ports do not reliably
> update PME status registers (PME Status and PME Requester_ID in the
> Root Status register) during D3hot to D0 transitions, even though PME
> interrupts are delivered correctly.
[...]
> Work around this issue by introducing a PCI_DEV_FLAGS_PME_UNRELIABLE
> flag for affected ports. When this flag is set, pciehp keeps hotplug
> interrupts (HPIE) enabled during D3hot instead of disabling them and
> relying on PME. This allows hotplug events to be delivered via direct
> interrupts rather than through the broken PME status mechanism.
[...]
> drivers/pci/hotplug/pciehp_core.c | 11 ++++--
> drivers/pci/quirks.c | 60 +++++++++++++++++++++++++++++++
> include/linux/pci.h | 2 ++
> 3 files changed, 71 insertions(+), 2 deletions(-)

Just one minor nit, the lines added to drivers/pci/quirks.c should
really be added to arch/x86/pci/fixup.c (or alternatively
arch/x86/kernel/quirks.c) because they only affect x86 platforms
and do not need to be compiled into the kernel on other arches.

We've had complaints in the past from people with low-memory mips
routers that the quirks needlessly occupy too much space:

https://lore.kernel.org/all/1482306784-29224-1-git-send-email-john@phrozen.org/

With that addressed,
Reviewed-by: Lukas Wunner <lukas@wunner.de>