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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4872716799dsm32314725e9.25.2026.03.28.03.08.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Mar 2026 03:08:39 -0700 (PDT) Date: Sat, 28 Mar 2026 10:08:37 +0000 From: David Laight To: Pawan Gupta Cc: Borislav Petkov , x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: Re: [PATCH v8 02/10] x86/bhi: Make clear_bhb_loop() effective on newer CPUs Message-ID: <20260328100837.7e6dc7fe@pumpkin> In-Reply-To: <20260328004256.mm2ttj5iwvu5kdpa@desk> References: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> <20260324-vmscape-bhb-v8-2-68bb524b3ab9@linux.intel.com> <20260324205930.GQacL7Mp7vwGBKX1W7@fat_crate.local> <20260324221308.7sh6afdy6r6tsf4w@desk> <20260325203759.GCacRHp2t8a7c4Bp6E@fat_crate.local> <20260326083934.fk4wyhe6rgiss34z@desk> <20260326100120.GAacUD8BVziYzLxZHB@fat_crate.local> <20260326104557.24295cbb@pumpkin> <20260326202931.wlggnd3nfj6hngpb@desk> <20260328004256.mm2ttj5iwvu5kdpa@desk> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Fri, 27 Mar 2026 17:42:56 -0700 Pawan Gupta wrote: > On Thu, Mar 26, 2026 at 01:29:31PM -0700, Pawan Gupta wrote: > > On Thu, Mar 26, 2026 at 10:45:57AM +0000, David Laight wrote: > > > On Thu, 26 Mar 2026 11:01:20 +0100 > > > Borislav Petkov wrote: > > > > > > > On Thu, Mar 26, 2026 at 01:39:34AM -0700, Pawan Gupta wrote: > > > > > I believe the equivalent for cpu_feature_enabled() in asm is the > > > > > ALTERNATIVE. Please let me know if I am missing something. > > > > > > > > Yes, you are. > > > > > > > > The point is that you don't want to stick those alternative calls inside some > > > > magic bhb_loop function but hand them in from the outside, as function > > > > arguments. > > > > > > > > Basically what I did. > > > > > > > > Then you were worried about this being C code and it had to be noinstr... So > > > > that outer function can be rewritten in asm, I think, and still keep it well > > > > separate. > > > > > > > > I'll try to rewrite it once I get a free minute, and see how it looks. > > > > > > > > > > I think someone tried getting C code to write the values to global data > > > and getting the asm to read them. > > > That got discounted because it spilt things between two largely unrelated files. > > > > > > The implementation with global variables wasn't that bad, let me revive it. > > > > This part which ties sequence to BHI mitigation, which is not ideal, > > (because VMSCAPE also uses it) it does seems a cleaner option. > > > > --- a/arch/x86/kernel/cpu/bugs.c > > +++ b/arch/x86/kernel/cpu/bugs.c > > @@ -2095,6 +2095,11 @@ static void __init bhi_select_mitigation(void) > > > > static void __init bhi_update_mitigation(void) > > { > > + if (!cpu_feature_enabled(X86_FEATURE_BHI_CTRL)) { > > + bhi_seq_outer_loop = 5; > > + bhi_seq_inner_loop = 5; > > + } > > + > > > > I believe this can be moved to somewhere common to all mitigations. > > > > > I think the BPF code would need significant refactoring to call a C function. > > > > Ya, true. Will use globals and keep clear_bhb_loop() in asm. > > While testing this approach, I noticed that syscalls were suffering an 8% > regression on ICX for Native BHI mitigation: > > $ perf bench syscall basic -l 100000000 > > Bisection pointed to the change for using 8-bit registers (al/ah replacing > eax/ecx) as the main contributor to the regression. (Global variables added > a bit, but within noise). > > Further digging revealed a strange behavior, using %ah for the inner loop > was causing the regression, interchanging %al and %ah in the loops > (for movb and sub) eliminated the regression. > > : > > movb bhb_seq_outer_loop(%rip), %al > > call 1f > jmp 5f > 1: call 2f > .Lret1: RET > 2: movb bhb_seq_inner_loop(%rip), %ah > 3: jmp 4f > nop > 4: sub $1, %ah <---- No regression with %al here > jnz 3b > sub $1, %al > jnz 1b > > My guess is, "sub $1, %al" is faster than "sub $1, %ah". Using %al in the > inner loop, which is executed more number of times is likely making the > difference. A perf profile is needed to confirm this. I bet it is also CPU dependant - it is quite likely that there isn't any special hardware to support partial writes of %ah so it ends up taking a slow path (possibly even a microcoded one to get an 8% regression). As well as swapping %al <-> %ah try changing the outer loop decrement to sub $0x100, %ax since %al is zero that will set the z flag the same. I've just hacked a test into some test code I've got. I'm not seeing an unexpected costs on either zen-5 or haswell. So it may be more subtle. David > > Never imagined a register selection can make an 8% difference in > performance! Anyways, will update the patch with this finding.