From: Lisa Robinson <lisa@bytefly.space>
To: Huacai Chen <chenhuacai@kernel.org>, WANG Xuerui <kernel@xen0n.name>
Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org,
Lisa Robinson <lisa@bytefly.space>
Subject: [PATCH] LoongArch: Align FPU register state to 32 bytes
Date: Mon, 30 Mar 2026 17:48:45 +0800 [thread overview]
Message-ID: <20260330094845.39-1-lisa@bytefly.space> (raw)
Move fpr to the beginning of struct loongarch_fpu so it is naturally
aligned to FPU_ALIGN (32 bytes), improving 256-bit SIMD (LASX) context
switch performance.
Signed-off-by: Lisa Robinson <lisa@bytefly.space>
---
arch/loongarch/include/asm/processor.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/loongarch/include/asm/processor.h b/arch/loongarch/include/asm/processor.h
index c3bc44b5f5b3..ce8b953f8c79 100644
--- a/arch/loongarch/include/asm/processor.h
+++ b/arch/loongarch/include/asm/processor.h
@@ -80,10 +80,10 @@ BUILD_FPR_ACCESS(32)
BUILD_FPR_ACCESS(64)
struct loongarch_fpu {
+ union fpureg fpr[NUM_FPU_REGS];
uint64_t fcc; /* 8x8 */
uint32_t fcsr;
uint32_t ftop;
- union fpureg fpr[NUM_FPU_REGS];
};
struct loongarch_lbt {
--
2.53.0
reply other threads:[~2026-03-30 9:48 UTC|newest]
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