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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2ca7cf010d7sm1287044eec.25.2026.04.01.20.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2026 20:01:39 -0700 (PDT) From: Francisco Munoz Ruiz Date: Wed, 01 Apr 2026 20:01:34 -0700 Subject: [PATCH 1/3] dt-bindings: cache: qcom,llcc: Document Hawi and future SoCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260401-external_llcc_changes2set-v1-1-97645ede9f6a@oss.qualcomm.com> References: <20260401-external_llcc_changes2set-v1-0-97645ede9f6a@oss.qualcomm.com> In-Reply-To: <20260401-external_llcc_changes2set-v1-0-97645ede9f6a@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Conor Dooley , Jonathan Cameron , Rob Herring , Kees Cook , "Gustavo A. R. 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Introduce a property that specifies the base address of the shared memory region from which the driver should read SCT descriptors provided by firmware. Signed-off-by: Francisco Munoz Ruiz Reviewed-by: Konrad Dybcio --- .../devicetree/bindings/cache/qcom,llcc.yaml | 29 ++++++++++++++++++---- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index 995d57815781..ca1313de10ca 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -11,16 +11,17 @@ maintainers: description: | LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, - that can be shared by multiple clients. Clients here are different cores in the - SoC, the idea is to minimize the local caches at the clients and migrate to - common pool of memory. Cache memory is divided into partitions called slices - which are assigned to clients. Clients can query the slice details, activate - and deactivate them. + that can be shared by multiple clients. Clients here are different cores in + the SoC. The idea is to minimize the local caches at the clients and migrate + to a common pool of memory. Cache memory is divided into partitions called + slices which are assigned to clients. Clients can query the slice details, + activate and deactivate them. properties: compatible: enum: - qcom,glymur-llcc + - qcom,hawi-llcc - qcom,ipq5424-llcc - qcom,kaanapali-llcc - qcom,qcs615-llcc @@ -57,6 +58,11 @@ properties: interrupts: maxItems: 1 + memory-region: + maxItems: 1 + description: handle to a reserved-memory node used for firmware-populated + SLC/SCT shared memory. + nvmem-cells: items: - description: Reference to an nvmem node for multi channel DDR @@ -318,6 +324,7 @@ allOf: contains: enum: - qcom,kaanapali-llcc + - qcom,hawi-llcc - qcom,sm8450-llcc - qcom,sm8550-llcc - qcom,sm8650-llcc @@ -340,6 +347,18 @@ allOf: - const: llcc3_base - const: llcc_broadcast_base - const: llcc_broadcast_and_base + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-llcc + then: + required: + - memory-region + else: + properties: + memory-region: false additionalProperties: false -- 2.34.1