* [PATCH 1/4] net: ionic: register PHC for rdma timestamping
2026-04-01 10:24 [PATCH 0/4] ionic: RDMA completion timestamping support Abhijit Gangurde
@ 2026-04-01 10:24 ` Abhijit Gangurde
2026-04-01 10:24 ` [PATCH 2/4] net: ionic: Add PHC state page for user space access Abhijit Gangurde
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Abhijit Gangurde @ 2026-04-01 10:24 UTC (permalink / raw)
To: jgg, leon, brett.creeley, andrew+netdev, davem, edumazet, kuba,
pabeni
Cc: allen.hubbe, nikhil.agarwal, linux-rdma, netdev, linux-kernel,
Abhijit Gangurde
Currently, the driver only registers the PTP Hardware Clock (PHC) if
Ethernet hardware timestamping is supported. Update the registration
logic to register the PHC if the device supports either Ethernet
hardware timestamping or RDMA completion timestamping.
Co-developed-by: Allen Hubbe <allen.hubbe@amd.com>
Signed-off-by: Allen Hubbe <allen.hubbe@amd.com>
Signed-off-by: Abhijit Gangurde <abhijit.gangurde@amd.com>
---
.../net/ethernet/pensando/ionic/ionic_if.h | 1 +
.../net/ethernet/pensando/ionic/ionic_lif.c | 5 ++++-
.../net/ethernet/pensando/ionic/ionic_phc.c | 20 ++++++++++++-------
3 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_if.h b/drivers/net/ethernet/pensando/ionic/ionic_if.h
index 47559c909c8b..3c34d5913729 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_if.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_if.h
@@ -1179,6 +1179,7 @@ enum ionic_eth_hw_features {
IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18),
IONIC_ETH_HW_TSO_GENEVE = BIT(19),
IONIC_ETH_HW_TIMESTAMP = BIT(20),
+ IONIC_ETH_HW_RDMA_TIMESTAMP = BIT(21),
};
/**
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
index 637e635bbf03..9d86f795f5f6 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
@@ -1498,7 +1498,8 @@ static int ionic_set_nic_features(struct ionic_lif *lif,
ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features);
if (lif->phc)
- ctx.cmd.lif_setattr.features |= cpu_to_le64(IONIC_ETH_HW_TIMESTAMP);
+ ctx.cmd.lif_setattr.features |= lif->ionic->ident.lif.eth.config.features &
+ cpu_to_le64(IONIC_ETH_HW_TIMESTAMP | IONIC_ETH_HW_RDMA_TIMESTAMP);
err = ionic_adminq_post_wait(lif, &ctx);
if (err)
@@ -1549,6 +1550,8 @@ static int ionic_set_nic_features(struct ionic_lif *lif,
dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n");
if (lif->hw_features & IONIC_ETH_HW_TIMESTAMP)
dev_dbg(dev, "feature ETH_HW_TIMESTAMP\n");
+ if (lif->hw_features & IONIC_ETH_HW_RDMA_TIMESTAMP)
+ dev_dbg(dev, "feature ETH_HW_RDMA_TIMESTAMP\n");
return 0;
}
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_phc.c b/drivers/net/ethernet/pensando/ionic/ionic_phc.c
index 05b44fc482f8..116408099974 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_phc.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_phc.c
@@ -77,7 +77,8 @@ static int ionic_lif_hwstamp_set_ts_config(struct ionic_lif *lif,
bool rx_all;
__le64 mask;
- if (!lif->phc || !lif->phc->ptp)
+ if (!lif->phc || !lif->phc->ptp ||
+ !(lif->hw_features & IONIC_ETH_HW_TIMESTAMP))
return -EOPNOTSUPP;
mutex_lock(&lif->phc->config_lock);
@@ -210,7 +211,8 @@ int ionic_hwstamp_set(struct net_device *netdev,
struct ionic_lif *lif = netdev_priv(netdev);
int err;
- if (!lif->phc || !lif->phc->ptp)
+ if (!lif->phc || !lif->phc->ptp ||
+ !(lif->hw_features & IONIC_ETH_HW_TIMESTAMP))
return -EOPNOTSUPP;
mutex_lock(&lif->queue_lock);
@@ -228,7 +230,8 @@ void ionic_lif_hwstamp_replay(struct ionic_lif *lif)
{
int err;
- if (!lif->phc || !lif->phc->ptp)
+ if (!lif->phc || !lif->phc->ptp ||
+ !(lif->hw_features & IONIC_ETH_HW_TIMESTAMP))
return;
mutex_lock(&lif->queue_lock);
@@ -242,7 +245,8 @@ void ionic_lif_hwstamp_recreate_queues(struct ionic_lif *lif)
{
int err;
- if (!lif->phc || !lif->phc->ptp)
+ if (!lif->phc || !lif->phc->ptp ||
+ !(lif->hw_features & IONIC_ETH_HW_TIMESTAMP))
return;
mutex_lock(&lif->phc->config_lock);
@@ -267,7 +271,8 @@ int ionic_hwstamp_get(struct net_device *netdev,
{
struct ionic_lif *lif = netdev_priv(netdev);
- if (!lif->phc || !lif->phc->ptp)
+ if (!lif->phc || !lif->phc->ptp ||
+ !(lif->hw_features & IONIC_ETH_HW_TIMESTAMP))
return -EOPNOTSUPP;
mutex_lock(&lif->phc->config_lock);
@@ -506,7 +511,8 @@ static const struct ptp_clock_info ionic_ptp_info = {
void ionic_lif_register_phc(struct ionic_lif *lif)
{
- if (!lif->phc || !(lif->hw_features & IONIC_ETH_HW_TIMESTAMP))
+ if (!lif->phc ||
+ !(lif->hw_features & (IONIC_ETH_HW_TIMESTAMP | IONIC_ETH_HW_RDMA_TIMESTAMP)))
return;
lif->phc->ptp = ptp_clock_register(&lif->phc->ptp_info, lif->ionic->dev);
@@ -545,7 +551,7 @@ void ionic_lif_alloc_phc(struct ionic_lif *lif)
return;
features = le64_to_cpu(ionic->ident.lif.eth.config.features);
- if (!(features & IONIC_ETH_HW_TIMESTAMP))
+ if (!(features & (IONIC_ETH_HW_TIMESTAMP | IONIC_ETH_HW_RDMA_TIMESTAMP)))
return;
phc = devm_kzalloc(ionic->dev, sizeof(*phc), GFP_KERNEL);
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/4] net: ionic: Add PHC state page for user space access
2026-04-01 10:24 [PATCH 0/4] ionic: RDMA completion timestamping support Abhijit Gangurde
2026-04-01 10:24 ` [PATCH 1/4] net: ionic: register PHC for rdma timestamping Abhijit Gangurde
@ 2026-04-01 10:24 ` Abhijit Gangurde
2026-04-02 0:06 ` Jakub Kicinski
2026-04-01 10:25 ` [PATCH 3/4] RDMA/ionic: map PHC state into user space Abhijit Gangurde
2026-04-01 10:25 ` [PATCH 4/4] RDMA/ionic: add completion timestamp to CQE format Abhijit Gangurde
3 siblings, 1 reply; 6+ messages in thread
From: Abhijit Gangurde @ 2026-04-01 10:24 UTC (permalink / raw)
To: jgg, leon, brett.creeley, andrew+netdev, davem, edumazet, kuba,
pabeni
Cc: allen.hubbe, nikhil.agarwal, linux-rdma, netdev, linux-kernel,
Abhijit Gangurde
Add a page associated with the PHC that can be mapped to user space,
allowing applications to access hardware timestamp information.
In order to synchronize between kernel and user space, a sequence
number is incremented at the beginning and end of each update.
An odd number means the data is being updated while an even number
means the update is complete. To guarantee that the data structure
was accessed atomically, user space will:
repeat:
seq1 = <read sequence>
goto <repeat> if odd
<read PHC state>
seq2 = <read sequence>
if seq1 != seq2 goto repeat
This mechanism acts as a guard against reading invalid state during
concurrent updates.
Co-developed-by: Allen Hubbe <allen.hubbe@amd.com>
Signed-off-by: Allen Hubbe <allen.hubbe@amd.com>
Signed-off-by: Abhijit Gangurde <abhijit.gangurde@amd.com>
---
.../net/ethernet/pensando/ionic/ionic_lif.h | 3 +-
.../net/ethernet/pensando/ionic/ionic_phc.c | 41 +++++++++++++++++++
include/uapi/rdma/ionic-abi.h | 11 +++++
3 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
index 8e10f66dc50e..0b820af2b523 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
@@ -249,7 +249,7 @@ struct ionic_lif {
};
struct ionic_phc {
- spinlock_t lock; /* lock for cc and tc */
+ spinlock_t lock; /* lock for state_page, cc and tc */
struct cyclecounter cc;
struct timecounter tc;
@@ -262,6 +262,7 @@ struct ionic_phc {
long aux_work_delay;
struct ptp_clock_info ptp_info;
+ struct ionic_phc_state *state_page;
struct ptp_clock *ptp;
struct ionic_lif *lif;
};
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_phc.c b/drivers/net/ethernet/pensando/ionic/ionic_phc.c
index 116408099974..61eaf3834608 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_phc.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_phc.c
@@ -3,6 +3,7 @@
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
+#include <rdma/ionic-abi.h>
#include "ionic.h"
#include "ionic_bus.h"
@@ -334,6 +335,26 @@ static int ionic_setphc_cmd(struct ionic_phc *phc, struct ionic_admin_ctx *ctx)
return ionic_adminq_post(phc->lif, ctx);
}
+static void ionic_phc_state_page_update(struct ionic_phc *phc)
+{
+ struct ionic_phc_state *state = phc->state_page;
+ u32 seq;
+
+ /* read current seq */
+ seq = smp_load_acquire(&state->seq) & ~1;
+
+ /* make seq odd for updating */
+ smp_store_mb(state->seq, seq | 1);
+
+ state->tick = phc->tc.cycle_last;
+ state->nsec = phc->tc.nsec;
+ state->frac = phc->tc.frac;
+ state->mult = phc->cc.mult;
+
+ /* make seq the next even number for update completed */
+ smp_store_release(&state->seq, seq + 2);
+}
+
static int ionic_phc_adjfine(struct ptp_clock_info *info, long scaled_ppm)
{
struct ionic_phc *phc = container_of(info, struct ionic_phc, ptp_info);
@@ -361,6 +382,8 @@ static int ionic_phc_adjfine(struct ptp_clock_info *info, long scaled_ppm)
timecounter_read(&phc->tc);
phc->cc.mult = adj;
+ ionic_phc_state_page_update(phc);
+
/* Setphc commands are posted in-order, sequenced by phc->lock. We
* need to drop the lock before waiting for the command to complete.
*/
@@ -386,6 +409,8 @@ static int ionic_phc_adjtime(struct ptp_clock_info *info, s64 delta)
timecounter_adjtime(&phc->tc, delta);
+ ionic_phc_state_page_update(phc);
+
/* Setphc commands are posted in-order, sequenced by phc->lock. We
* need to drop the lock before waiting for the command to complete.
*/
@@ -415,6 +440,8 @@ static int ionic_phc_settime64(struct ptp_clock_info *info,
timecounter_init(&phc->tc, &phc->cc, ns);
+ ionic_phc_state_page_update(phc);
+
/* Setphc commands are posted in-order, sequenced by phc->lock. We
* need to drop the lock before waiting for the command to complete.
*/
@@ -472,6 +499,8 @@ static long ionic_phc_aux_work(struct ptp_clock_info *info)
/* update point-in-time basis to now */
timecounter_read(&phc->tc);
+ ionic_phc_state_page_update(phc);
+
/* Setphc commands are posted in-order, sequenced by phc->lock. We
* need to drop the lock before waiting for the command to complete.
*/
@@ -558,6 +587,12 @@ void ionic_lif_alloc_phc(struct ionic_lif *lif)
if (!phc)
return;
+ phc->state_page = (void *)get_zeroed_page(GFP_KERNEL);
+ if (!phc->state_page) {
+ devm_kfree(ionic->dev, phc);
+ return;
+ }
+
phc->lif = lif;
phc->cc.read = ionic_cc_read;
@@ -569,6 +604,7 @@ void ionic_lif_alloc_phc(struct ionic_lif *lif)
dev_err(lif->ionic->dev,
"Invalid device PHC mask multiplier %u, disabling HW timestamp support\n",
phc->cc.mult);
+ free_page((unsigned long)phc->state_page);
devm_kfree(lif->ionic->dev, phc);
lif->phc = NULL;
return;
@@ -652,6 +688,10 @@ void ionic_lif_alloc_phc(struct ionic_lif *lif)
*/
phc->ptp_info.max_adj = NORMAL_PPB;
+ phc->state_page->mask = phc->cc.mask;
+ phc->state_page->shift = phc->cc.shift;
+ ionic_phc_state_page_update(phc);
+
lif->phc = phc;
}
@@ -662,6 +702,7 @@ void ionic_lif_free_phc(struct ionic_lif *lif)
mutex_destroy(&lif->phc->config_lock);
+ free_page((unsigned long)lif->phc->state_page);
devm_kfree(lif->ionic->dev, lif->phc);
lif->phc = NULL;
}
diff --git a/include/uapi/rdma/ionic-abi.h b/include/uapi/rdma/ionic-abi.h
index 7b589d3e9728..97f695510380 100644
--- a/include/uapi/rdma/ionic-abi.h
+++ b/include/uapi/rdma/ionic-abi.h
@@ -112,4 +112,15 @@ struct ionic_srq_resp {
__aligned_u64 rq_cmb_offset;
};
+struct ionic_phc_state {
+ __u32 seq;
+ __u32 rsvd;
+ __aligned_u64 mask;
+ __aligned_u64 tick;
+ __aligned_u64 nsec;
+ __aligned_u64 frac;
+ __u32 mult;
+ __u32 shift;
+};
+
#endif /* IONIC_ABI_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 2/4] net: ionic: Add PHC state page for user space access
2026-04-01 10:24 ` [PATCH 2/4] net: ionic: Add PHC state page for user space access Abhijit Gangurde
@ 2026-04-02 0:06 ` Jakub Kicinski
0 siblings, 0 replies; 6+ messages in thread
From: Jakub Kicinski @ 2026-04-02 0:06 UTC (permalink / raw)
To: Abhijit Gangurde
Cc: jgg, leon, brett.creeley, andrew+netdev, davem, edumazet, pabeni,
allen.hubbe, nikhil.agarwal, linux-rdma, netdev, linux-kernel
On Wed, 1 Apr 2026 15:54:59 +0530 Abhijit Gangurde wrote:
> diff --git a/include/uapi/rdma/ionic-abi.h b/include/uapi/rdma/ionic-abi.h
> index 7b589d3e9728..97f695510380 100644
> --- a/include/uapi/rdma/ionic-abi.h
> +++ b/include/uapi/rdma/ionic-abi.h
> @@ -112,4 +112,15 @@ struct ionic_srq_resp {
> __aligned_u64 rq_cmb_offset;
> };
>
> +struct ionic_phc_state {
> + __u32 seq;
> + __u32 rsvd;
> + __aligned_u64 mask;
> + __aligned_u64 tick;
> + __aligned_u64 nsec;
> + __aligned_u64 frac;
> + __u32 mult;
> + __u32 shift;
> +};
You're just exposing kernel timecounter internals.
Why is this ionic uAPI and not something reusable by other drivers?
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/4] RDMA/ionic: map PHC state into user space
2026-04-01 10:24 [PATCH 0/4] ionic: RDMA completion timestamping support Abhijit Gangurde
2026-04-01 10:24 ` [PATCH 1/4] net: ionic: register PHC for rdma timestamping Abhijit Gangurde
2026-04-01 10:24 ` [PATCH 2/4] net: ionic: Add PHC state page for user space access Abhijit Gangurde
@ 2026-04-01 10:25 ` Abhijit Gangurde
2026-04-01 10:25 ` [PATCH 4/4] RDMA/ionic: add completion timestamp to CQE format Abhijit Gangurde
3 siblings, 0 replies; 6+ messages in thread
From: Abhijit Gangurde @ 2026-04-01 10:25 UTC (permalink / raw)
To: jgg, leon, brett.creeley, andrew+netdev, davem, edumazet, kuba,
pabeni
Cc: allen.hubbe, nikhil.agarwal, linux-rdma, netdev, linux-kernel,
Abhijit Gangurde
Enable user space applications to access the PHC state page when
firmware RDMA completion timestamp is supported.
This mapping allows user space to convert RDMA completion timestamps
to system wall time without kernel transitions, minimizing latency
overhead. Applications can directly read the PHC state through mmap,
enabling efficient timestamp correlation for precision timing
applications.
Co-developed-by: Allen Hubbe <allen.hubbe@amd.com>
Signed-off-by: Allen Hubbe <allen.hubbe@amd.com>
Signed-off-by: Abhijit Gangurde <abhijit.gangurde@amd.com>
---
.../infiniband/hw/ionic/ionic_controlpath.c | 36 ++++++++++++++++++-
drivers/infiniband/hw/ionic/ionic_ibdev.h | 2 ++
drivers/infiniband/hw/ionic/ionic_lif_cfg.c | 2 ++
drivers/infiniband/hw/ionic/ionic_lif_cfg.h | 1 +
include/uapi/rdma/ionic-abi.h | 1 +
5 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/drivers/infiniband/hw/ionic/ionic_controlpath.c b/drivers/infiniband/hw/ionic/ionic_controlpath.c
index a5671da3db64..5a0b189f9855 100644
--- a/drivers/infiniband/hw/ionic/ionic_controlpath.c
+++ b/drivers/infiniband/hw/ionic/ionic_controlpath.c
@@ -391,6 +391,16 @@ int ionic_alloc_ucontext(struct ib_ucontext *ibctx, struct ib_udata *udata)
goto err_mmap_dbell;
}
+ if (dev->lif_cfg.phc_state) {
+ ctx->mmap_phc = ionic_mmap_entry_insert(ctx, PAGE_SIZE, 0,
+ IONIC_MMAP_PHC,
+ &resp.phc_offset);
+ if (!ctx->mmap_phc) {
+ rc = -ENOMEM;
+ goto err_mmap_phc;
+ }
+ }
+
resp.page_shift = PAGE_SHIFT;
resp.dbell_offset = db_phys & ~PAGE_MASK;
@@ -414,13 +424,15 @@ int ionic_alloc_ucontext(struct ib_ucontext *ibctx, struct ib_udata *udata)
if (dev->lif_cfg.rq_expdb)
resp.expdb_qtypes |= IONIC_EXPDB_RQ;
- rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
+ rc = ib_respond_udata(udata, resp);
if (rc)
goto err_resp;
return 0;
err_resp:
+ rdma_user_mmap_entry_remove(ctx->mmap_phc);
+err_mmap_phc:
rdma_user_mmap_entry_remove(ctx->mmap_dbell);
err_mmap_dbell:
ionic_put_dbid(dev, ctx->dbid);
@@ -433,10 +445,26 @@ void ionic_dealloc_ucontext(struct ib_ucontext *ibctx)
struct ionic_ibdev *dev = to_ionic_ibdev(ibctx->device);
struct ionic_ctx *ctx = to_ionic_ctx(ibctx);
+ rdma_user_mmap_entry_remove(ctx->mmap_phc);
rdma_user_mmap_entry_remove(ctx->mmap_dbell);
ionic_put_dbid(dev, ctx->dbid);
}
+static int ionic_mmap_phc_stage(struct ionic_ibdev *dev,
+ struct vm_area_struct *vma)
+{
+ if (!(vma->vm_flags & VM_SHARED))
+ return -EINVAL;
+
+ if (vma->vm_flags & (VM_WRITE | VM_EXEC))
+ return -EPERM;
+
+ vm_flags_clear(vma, VM_MAYWRITE);
+
+ return vm_insert_page(vma, vma->vm_start,
+ virt_to_page(dev->lif_cfg.phc_state));
+}
+
int ionic_mmap(struct ib_ucontext *ibctx, struct vm_area_struct *vma)
{
struct ionic_ibdev *dev = to_ionic_ibdev(ibctx->device);
@@ -455,6 +483,12 @@ int ionic_mmap(struct ib_ucontext *ibctx, struct vm_area_struct *vma)
ionic_entry = container_of(rdma_entry, struct ionic_mmap_entry,
rdma_entry);
+ if (ionic_entry->mmap_flags & IONIC_MMAP_PHC) {
+ rc = ionic_mmap_phc_stage(dev, vma);
+ rdma_user_mmap_entry_put(rdma_entry);
+ return rc;
+ }
+
ibdev_dbg(&dev->ibdev, "writecombine? %d\n",
ionic_entry->mmap_flags & IONIC_MMAP_WC);
if (ionic_entry->mmap_flags & IONIC_MMAP_WC)
diff --git a/drivers/infiniband/hw/ionic/ionic_ibdev.h b/drivers/infiniband/hw/ionic/ionic_ibdev.h
index 63828240d659..08655c4d8297 100644
--- a/drivers/infiniband/hw/ionic/ionic_ibdev.h
+++ b/drivers/infiniband/hw/ionic/ionic_ibdev.h
@@ -72,6 +72,7 @@ enum ionic_admin_flags {
enum ionic_mmap_flag {
IONIC_MMAP_WC = BIT(0),
+ IONIC_MMAP_PHC = BIT(1),
};
struct ionic_mmap_entry {
@@ -173,6 +174,7 @@ struct ionic_ctx {
struct ib_ucontext ibctx;
u32 dbid;
struct rdma_user_mmap_entry *mmap_dbell;
+ struct rdma_user_mmap_entry *mmap_phc;
};
struct ionic_tbl_buf {
diff --git a/drivers/infiniband/hw/ionic/ionic_lif_cfg.c b/drivers/infiniband/hw/ionic/ionic_lif_cfg.c
index f3cd281c3a2f..e3f2df1f9e6a 100644
--- a/drivers/infiniband/hw/ionic/ionic_lif_cfg.c
+++ b/drivers/infiniband/hw/ionic/ionic_lif_cfg.c
@@ -40,6 +40,8 @@ void ionic_fill_lif_cfg(struct ionic_lif *lif, struct ionic_lif_cfg *cfg)
cfg->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif);
cfg->dbpage = lif->kern_dbpage;
cfg->intr_ctrl = lif->ionic->idev.intr_ctrl;
+ if (ident->eth.config.features & cpu_to_le64(IONIC_ETH_HW_RDMA_TIMESTAMP))
+ cfg->phc_state = lif->phc->state_page;
cfg->db_phys = lif->ionic->bars[IONIC_PCI_BAR_DBELL].bus_addr;
diff --git a/drivers/infiniband/hw/ionic/ionic_lif_cfg.h b/drivers/infiniband/hw/ionic/ionic_lif_cfg.h
index 20853429f623..2b29e646c193 100644
--- a/drivers/infiniband/hw/ionic/ionic_lif_cfg.h
+++ b/drivers/infiniband/hw/ionic/ionic_lif_cfg.h
@@ -23,6 +23,7 @@ struct ionic_lif_cfg {
u64 __iomem *dbpage;
struct ionic_intr __iomem *intr_ctrl;
phys_addr_t db_phys;
+ void *phc_state;
u64 page_size_supported;
u32 npts_per_lif;
diff --git a/include/uapi/rdma/ionic-abi.h b/include/uapi/rdma/ionic-abi.h
index 97f695510380..abd1bde0991f 100644
--- a/include/uapi/rdma/ionic-abi.h
+++ b/include/uapi/rdma/ionic-abi.h
@@ -48,6 +48,7 @@ struct ionic_ctx_resp {
__u8 expdb_qtypes;
__u8 rsvd2[3];
+ __aligned_u64 phc_offset;
};
struct ionic_qdesc {
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 4/4] RDMA/ionic: add completion timestamp to CQE format
2026-04-01 10:24 [PATCH 0/4] ionic: RDMA completion timestamping support Abhijit Gangurde
` (2 preceding siblings ...)
2026-04-01 10:25 ` [PATCH 3/4] RDMA/ionic: map PHC state into user space Abhijit Gangurde
@ 2026-04-01 10:25 ` Abhijit Gangurde
3 siblings, 0 replies; 6+ messages in thread
From: Abhijit Gangurde @ 2026-04-01 10:25 UTC (permalink / raw)
To: jgg, leon, brett.creeley, andrew+netdev, davem, edumazet, kuba,
pabeni
Cc: allen.hubbe, nikhil.agarwal, linux-rdma, netdev, linux-kernel,
Abhijit Gangurde
Update the CQE structure to include hardware timestamp.
When firmware supports RDMA completion timestamps,
the hardware populates the timestamp field.
Co-developed-by: Allen Hubbe <allen.hubbe@amd.com>
Signed-off-by: Allen Hubbe <allen.hubbe@amd.com>
Signed-off-by: Abhijit Gangurde <abhijit.gangurde@amd.com>
---
drivers/infiniband/hw/ionic/ionic_datapath.c | 43 ++++++++++----------
drivers/infiniband/hw/ionic/ionic_fw.h | 12 ++++--
2 files changed, 31 insertions(+), 24 deletions(-)
diff --git a/drivers/infiniband/hw/ionic/ionic_datapath.c b/drivers/infiniband/hw/ionic/ionic_datapath.c
index aa2944887f23..3e2300f7ea10 100644
--- a/drivers/infiniband/hw/ionic/ionic_datapath.c
+++ b/drivers/infiniband/hw/ionic/ionic_datapath.c
@@ -32,6 +32,7 @@ static int ionic_flush_recv(struct ionic_qp *qp, struct ib_wc *wc)
{
struct ionic_rq_meta *meta;
struct ionic_v1_wqe *wqe;
+ u64 wqe_idx;
if (!qp->rq_flush)
return 0;
@@ -40,21 +41,22 @@ static int ionic_flush_recv(struct ionic_qp *qp, struct ib_wc *wc)
return 0;
wqe = ionic_queue_at_cons(&qp->rq);
+ wqe_idx = le64_to_cpu(wqe->base.wqe_idx);
- /* wqe_id must be a valid queue index */
- if (unlikely(wqe->base.wqe_id >> qp->rq.depth_log2)) {
+ /* wqe_idx must be a valid queue index */
+ if (unlikely(wqe_idx >> qp->rq.depth_log2)) {
ibdev_warn(qp->ibqp.device,
"flush qp %u recv index %llu invalid\n",
- qp->qpid, (unsigned long long)wqe->base.wqe_id);
+ qp->qpid, (unsigned long long)wqe_idx);
return -EIO;
}
- /* wqe_id must indicate a request that is outstanding */
- meta = &qp->rq_meta[wqe->base.wqe_id];
+ /* wqe_idx must indicate a request that is outstanding */
+ meta = &qp->rq_meta[wqe_idx];
if (unlikely(meta->next != IONIC_META_POSTED)) {
ibdev_warn(qp->ibqp.device,
"flush qp %u recv index %llu not posted\n",
- qp->qpid, (unsigned long long)wqe->base.wqe_id);
+ qp->qpid, (unsigned long long)wqe_idx);
return -EIO;
}
@@ -133,8 +135,8 @@ static int ionic_poll_recv(struct ionic_ibdev *dev, struct ionic_cq *cq,
{
struct ionic_qp *qp = NULL;
struct ionic_rq_meta *meta;
+ u16 vlan_tag, wqe_idx;
u32 src_qpn, st_len;
- u16 vlan_tag;
u8 op;
if (cqe_qp->rq_flush)
@@ -144,7 +146,7 @@ static int ionic_poll_recv(struct ionic_ibdev *dev, struct ionic_cq *cq,
st_len = be32_to_cpu(cqe->status_length);
- /* ignore wqe_id in case of flush error */
+ /* ignore wqe_idx in case of flush error */
if (ionic_v1_cqe_error(cqe) && st_len == IONIC_STS_WQE_FLUSHED_ERR) {
cqe_qp->rq_flush = true;
cq->flush = true;
@@ -160,20 +162,19 @@ static int ionic_poll_recv(struct ionic_ibdev *dev, struct ionic_cq *cq,
return -EIO;
}
- /* wqe_id must be a valid queue index */
- if (unlikely(cqe->recv.wqe_id >> qp->rq.depth_log2)) {
+ wqe_idx = le64_to_cpu(cqe->recv.wqe_idx_timestamp) & IONIC_V1_CQE_WQE_IDX_MASK;
+ /* wqe_idx must be a valid queue index */
+ if (unlikely(wqe_idx >> qp->rq.depth_log2)) {
ibdev_warn(&dev->ibdev,
- "qp %u recv index %llu invalid\n",
- qp->qpid, (unsigned long long)cqe->recv.wqe_id);
+ "qp %u recv index %u invalid\n", qp->qpid, wqe_idx);
return -EIO;
}
- /* wqe_id must indicate a request that is outstanding */
- meta = &qp->rq_meta[cqe->recv.wqe_id];
+ /* wqe_idx must indicate a request that is outstanding */
+ meta = &qp->rq_meta[wqe_idx];
if (unlikely(meta->next != IONIC_META_POSTED)) {
ibdev_warn(&dev->ibdev,
- "qp %u recv index %llu not posted\n",
- qp->qpid, (unsigned long long)cqe->recv.wqe_id);
+ "qp %u recv index %u not posted\n", qp->qpid, wqe_idx);
return -EIO;
}
@@ -408,7 +409,7 @@ static int ionic_comp_msn(struct ionic_qp *qp, struct ionic_v1_cqe *cqe)
static int ionic_comp_npg(struct ionic_qp *qp, struct ionic_v1_cqe *cqe)
{
struct ionic_sq_meta *meta;
- u16 cqe_idx;
+ u16 wqe_idx;
u32 st_len;
if (qp->sq_flush)
@@ -430,8 +431,8 @@ static int ionic_comp_npg(struct ionic_qp *qp, struct ionic_v1_cqe *cqe)
return 0;
}
- cqe_idx = cqe->send.npg_wqe_id & qp->sq.mask;
- meta = &qp->sq_meta[cqe_idx];
+ wqe_idx = le64_to_cpu(cqe->send.npg_wqe_idx_timestamp) & qp->sq.mask;
+ meta = &qp->sq_meta[wqe_idx];
meta->local_comp = true;
if (ionic_v1_cqe_error(cqe)) {
@@ -811,7 +812,7 @@ static void ionic_prep_base(struct ionic_qp *qp,
meta->signal = false;
meta->local_comp = false;
- wqe->base.wqe_id = qp->sq.prod;
+ wqe->base.wqe_idx = cpu_to_le64(qp->sq.prod);
if (wr->send_flags & IB_SEND_FENCE)
wqe->base.flags |= cpu_to_be16(IONIC_V1_FLAG_FENCE);
@@ -1205,7 +1206,7 @@ static int ionic_prep_recv(struct ionic_qp *qp,
meta->wrid = wr->wr_id;
- wqe->base.wqe_id = meta - qp->rq_meta;
+ wqe->base.wqe_idx = cpu_to_le64(meta - qp->rq_meta);
wqe->base.num_sge_key = wr->num_sge;
/* total length for recv goes in base imm_data_key */
diff --git a/drivers/infiniband/hw/ionic/ionic_fw.h b/drivers/infiniband/hw/ionic/ionic_fw.h
index adfbb89d856c..ee23062a1762 100644
--- a/drivers/infiniband/hw/ionic/ionic_fw.h
+++ b/drivers/infiniband/hw/ionic/ionic_fw.h
@@ -332,7 +332,7 @@ struct ionic_v1_cqe {
__le16 old_rq_cq_cindex;
} admin;
struct {
- __u64 wqe_id;
+ __le64 wqe_idx_timestamp;
__be32 src_qpn_op;
__u8 src_mac[6];
__be16 vlan_tag;
@@ -342,13 +342,19 @@ struct ionic_v1_cqe {
__u8 rsvd[4];
__be32 msg_msn;
__u8 rsvd2[8];
- __u64 npg_wqe_id;
+ __le64 npg_wqe_idx_timestamp;
} send;
};
__be32 status_length;
__be32 qid_type_flags;
};
+/* bits for cqe wqe_idx and timestamp */
+enum ionic_v1_cqe_wqe_idx_timestamp_bits {
+ IONIC_V1_CQE_WQE_IDX_MASK = 0xffff,
+ IONIC_V1_CQE_TIMESTAMP_SHIFT = 16,
+};
+
/* bits for cqe recv */
enum ionic_v1_cqe_src_qpn_bits {
IONIC_V1_CQE_RECV_QPN_MASK = 0xffffff,
@@ -423,7 +429,7 @@ static inline u32 ionic_v1_cqe_qtf_qid(u32 qtf)
/* v1 base wqe header */
struct ionic_v1_base_hdr {
- __u64 wqe_id;
+ __le64 wqe_idx;
__u8 op;
__u8 num_sge_key;
__be16 flags;
--
2.43.0
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