From: Lu Baolu <baolu.lu@linux.intel.com>
To: Joerg Roedel <joro@8bytes.org>
Cc: Zhenzhong Duan <zhenzhong.duan@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Jason Gunthorpe <jgg@nvidia.com>,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: [PATCH 07/10] iommu/vt-d: Split piotlb invalidation into range and all
Date: Thu, 2 Apr 2026 14:57:30 +0800 [thread overview]
Message-ID: <20260402065734.1687476-8-baolu.lu@linux.intel.com> (raw)
In-Reply-To: <20260402065734.1687476-1-baolu.lu@linux.intel.com>
From: Jason Gunthorpe <jgg@nvidia.com>
Currently these call chains are muddled up by using npages=-1, but only
one caller has the possibility to do both options.
Simplify qi_flush_piotlb() to qi_flush_piotlb_all() since all callers
pass npages=-1.
Split qi_batch_add_piotlb() into qi_batch_add_piotlb_all() and related
helpers.
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/1-v1-f175e27af136+11647-iommupt_inv_vtd_jgg@nvidia.com
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
drivers/iommu/intel/iommu.h | 39 +++++++++++++++++--------------------
drivers/iommu/intel/cache.c | 20 ++++++++++++-------
drivers/iommu/intel/dmar.c | 19 ++++--------------
drivers/iommu/intel/pasid.c | 6 +++---
drivers/iommu/intel/prq.c | 2 +-
5 files changed, 39 insertions(+), 47 deletions(-)
diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h
index 10331364c0ef..9b193bbcfd58 100644
--- a/drivers/iommu/intel/iommu.h
+++ b/drivers/iommu/intel/iommu.h
@@ -1077,31 +1077,29 @@ static inline void qi_desc_dev_iotlb(u16 sid, u16 pfsid, u16 qdep, u64 addr,
desc->qw3 = 0;
}
+/* PASID-selective IOTLB invalidation */
+static inline void qi_desc_piotlb_all(u16 did, u32 pasid, struct qi_desc *desc)
+{
+ desc->qw0 = QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) |
+ QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
+ desc->qw1 = 0;
+}
+
+/* Page-selective-within-PASID IOTLB invalidation */
static inline void qi_desc_piotlb(u16 did, u32 pasid, u64 addr,
unsigned long npages, bool ih,
struct qi_desc *desc)
{
- if (npages == -1) {
- desc->qw0 = QI_EIOTLB_PASID(pasid) |
- QI_EIOTLB_DID(did) |
- QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
- QI_EIOTLB_TYPE;
- desc->qw1 = 0;
- } else {
- int mask = ilog2(__roundup_pow_of_two(npages));
- unsigned long align = (1ULL << (VTD_PAGE_SHIFT + mask));
+ int mask = ilog2(__roundup_pow_of_two(npages));
+ unsigned long align = (1ULL << (VTD_PAGE_SHIFT + mask));
- if (WARN_ON_ONCE(!IS_ALIGNED(addr, align)))
- addr = ALIGN_DOWN(addr, align);
+ if (WARN_ON_ONCE(!IS_ALIGNED(addr, align)))
+ addr = ALIGN_DOWN(addr, align);
- desc->qw0 = QI_EIOTLB_PASID(pasid) |
- QI_EIOTLB_DID(did) |
- QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
- QI_EIOTLB_TYPE;
- desc->qw1 = QI_EIOTLB_ADDR(addr) |
- QI_EIOTLB_IH(ih) |
- QI_EIOTLB_AM(mask);
- }
+ desc->qw0 = QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) |
+ QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE;
+ desc->qw1 = QI_EIOTLB_ADDR(addr) | QI_EIOTLB_IH(ih) |
+ QI_EIOTLB_AM(mask);
}
static inline void qi_desc_dev_iotlb_pasid(u16 sid, u16 pfsid, u32 pasid,
@@ -1163,8 +1161,7 @@ void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
u16 qdep, u64 addr, unsigned mask);
-void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
- unsigned long npages, bool ih);
+void qi_flush_piotlb_all(struct intel_iommu *iommu, u16 did, u32 pasid);
void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
u32 pasid, u16 qdep, u64 addr,
diff --git a/drivers/iommu/intel/cache.c b/drivers/iommu/intel/cache.c
index 249ab5886c73..3ae0d21ecb9f 100644
--- a/drivers/iommu/intel/cache.c
+++ b/drivers/iommu/intel/cache.c
@@ -330,15 +330,17 @@ static void qi_batch_add_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid
qi_batch_increment_index(iommu, batch);
}
+static void qi_batch_add_piotlb_all(struct intel_iommu *iommu, u16 did,
+ u32 pasid, struct qi_batch *batch)
+{
+ qi_desc_piotlb_all(did, pasid, &batch->descs[batch->index]);
+ qi_batch_increment_index(iommu, batch);
+}
+
static void qi_batch_add_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid,
u64 addr, unsigned long npages, bool ih,
struct qi_batch *batch)
{
- /*
- * npages == -1 means a PASID-selective invalidation, otherwise,
- * a positive value for Page-selective-within-PASID invalidation.
- * 0 is not a valid input.
- */
if (!npages)
return;
@@ -378,8 +380,12 @@ static void cache_tag_flush_iotlb(struct dmar_domain *domain, struct cache_tag *
u64 type = DMA_TLB_PSI_FLUSH;
if (intel_domain_use_piotlb(domain)) {
- qi_batch_add_piotlb(iommu, tag->domain_id, tag->pasid, addr,
- pages, ih, domain->qi_batch);
+ if (pages == -1)
+ qi_batch_add_piotlb_all(iommu, tag->domain_id,
+ tag->pasid, domain->qi_batch);
+ else
+ qi_batch_add_piotlb(iommu, tag->domain_id, tag->pasid,
+ addr, pages, ih, domain->qi_batch);
return;
}
diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
index cd04c3f56eec..d33c119a935e 100644
--- a/drivers/iommu/intel/dmar.c
+++ b/drivers/iommu/intel/dmar.c
@@ -1550,23 +1550,12 @@ void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
qi_submit_sync(iommu, &desc, 1, 0);
}
-/* PASID-based IOTLB invalidation */
-void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
- unsigned long npages, bool ih)
+/* PASID-selective IOTLB invalidation */
+void qi_flush_piotlb_all(struct intel_iommu *iommu, u16 did, u32 pasid)
{
- struct qi_desc desc = {.qw2 = 0, .qw3 = 0};
+ struct qi_desc desc = {};
- /*
- * npages == -1 means a PASID-selective invalidation, otherwise,
- * a positive value for Page-selective-within-PASID invalidation.
- * 0 is not a valid input.
- */
- if (WARN_ON(!npages)) {
- pr_err("Invalid input npages = %ld\n", npages);
- return;
- }
-
- qi_desc_piotlb(did, pasid, addr, npages, ih, &desc);
+ qi_desc_piotlb_all(did, pasid, &desc);
qi_submit_sync(iommu, &desc, 1, 0);
}
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index 9d30015b8940..89541b74ab8c 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -282,7 +282,7 @@ void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev,
pasid_cache_invalidation_with_pasid(iommu, did, pasid);
if (pgtt == PASID_ENTRY_PGTT_PT || pgtt == PASID_ENTRY_PGTT_FL_ONLY)
- qi_flush_piotlb(iommu, did, pasid, 0, -1, 0);
+ qi_flush_piotlb_all(iommu, did, pasid);
else
iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH);
@@ -308,7 +308,7 @@ static void pasid_flush_caches(struct intel_iommu *iommu,
if (cap_caching_mode(iommu->cap)) {
pasid_cache_invalidation_with_pasid(iommu, did, pasid);
- qi_flush_piotlb(iommu, did, pasid, 0, -1, 0);
+ qi_flush_piotlb_all(iommu, did, pasid);
} else {
iommu_flush_write_buffer(iommu);
}
@@ -342,7 +342,7 @@ static void intel_pasid_flush_present(struct intel_iommu *iommu,
* Addr[63:12]=0x7FFFFFFF_FFFFF) to affected functions
*/
pasid_cache_invalidation_with_pasid(iommu, did, pasid);
- qi_flush_piotlb(iommu, did, pasid, 0, -1, 0);
+ qi_flush_piotlb_all(iommu, did, pasid);
devtlb_invalidation_with_pasid(iommu, dev, pasid);
}
diff --git a/drivers/iommu/intel/prq.c b/drivers/iommu/intel/prq.c
index 1460b57db129..586055e51bb2 100644
--- a/drivers/iommu/intel/prq.c
+++ b/drivers/iommu/intel/prq.c
@@ -113,7 +113,7 @@ void intel_iommu_drain_pasid_prq(struct device *dev, u32 pasid)
qi_desc_dev_iotlb(sid, info->pfsid, info->ats_qdep, 0,
MAX_AGAW_PFN_WIDTH, &desc[2]);
} else {
- qi_desc_piotlb(did, pasid, 0, -1, 0, &desc[1]);
+ qi_desc_piotlb_all(did, pasid, &desc[1]);
qi_desc_dev_iotlb_pasid(sid, info->pfsid, pasid, info->ats_qdep,
0, MAX_AGAW_PFN_WIDTH, &desc[2]);
}
--
2.43.0
next prev parent reply other threads:[~2026-04-02 7:00 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-02 6:57 [PATCH 00/10] [PULL REQUEST] Intel IOMMU updates for v7.1 Lu Baolu
2026-04-02 6:57 ` [PATCH 01/10] iommu/vt-d: Block PASID attachment to nested domain with dirty tracking Lu Baolu
2026-04-02 6:57 ` [PATCH 02/10] iommu/vt-d: Rename device_set_dirty_tracking() and pass dmar_domain pointer Lu Baolu
2026-04-02 6:57 ` [PATCH 03/10] iommu/vt-d: Support dirty tracking on PASID Lu Baolu
2026-04-02 6:57 ` [PATCH 04/10] iommufd/selftest: Test " Lu Baolu
2026-04-02 6:57 ` [PATCH 05/10] iommu/vt-d: Remove dmar_readl() and dmar_readq() Lu Baolu
2026-04-02 6:57 ` [PATCH 06/10] iommu/vt-d: Remove dmar_writel() and dmar_writeq() Lu Baolu
2026-04-02 6:57 ` Lu Baolu [this message]
2026-04-02 6:57 ` [PATCH 08/10] iommu/vt-d: Pass size_order to qi_desc_piotlb() not npages Lu Baolu
2026-04-02 6:57 ` [PATCH 09/10] iommu/vt-d: Remove the remaining pages along the invalidation path Lu Baolu
2026-04-02 6:57 ` [PATCH 10/10] iommu/vt-d: Simplify calculate_psi_aligned_address() Lu Baolu
2026-04-02 8:39 ` Baolu Lu
2026-04-02 9:46 ` Joerg Roedel
2026-04-02 15:35 ` Jason Gunthorpe
2026-04-02 7:26 ` [PATCH 00/10] [PULL REQUEST] Intel IOMMU updates for v7.1 Joerg Roedel
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