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From: Rob Herring <robh@kernel.org>
To: Qiang Yu <qiang.yu@oss.qualcomm.com>
Cc: Vinod Koul <vkoul@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add support for glymur Gen5 x8 bifurcation mode
Date: Tue, 7 Apr 2026 11:13:11 -0500	[thread overview]
Message-ID: <20260407161311.GA2666255-robh@kernel.org> (raw)
In-Reply-To: <20260323-glymur_gen5x8_phy_0323-v2-1-ce0fc07f0e52@oss.qualcomm.com>

On Mon, Mar 23, 2026 at 12:15:28AM -0700, Qiang Yu wrote:
> The Glymur SoC has pcie3a and pcie3b PHYs that can operate in two modes:
> 
> 1. Independent 4-lane mode: Each PHY operates as a separate PCIe Gen5
>    4-lane interface, compatible with qcom,glymur-qmp-gen5x4-pcie-phy
> 2. Bifurcation mode (8-lane): pcie3a phy acts as leader and pcie3b phy as
>    follower to form a single 8-lane PCIe Gen5 interface
> 
> In bifurcation mode, the hardware design requires controlling additional
> resources beyond the standard pcie3a PHY configuration:
> 
> - pcie3b's aux_clk (phy_b_aux)
> - pcie3b's phy_gdsc power domain
> - pcie3b's bcr/nocsr reset
> 
> Add qcom,glymur-qmp-gen5x8-pcie-phy compatible string to document this
> 8-lane bifurcation configuration.
> 
> The phy_b_aux clock is used as the 6th clock instead of pipediv2,
> requiring the clock-names enum to be extended to support both
> [phy_b_aux, pipediv2] options at index 5. This follows the existing
> pattern used for [rchng, refgen] clocks at index 3.
> 
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> ---
>  .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml   | 45 ++++++++++++++++++----
>  1 file changed, 37 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
> index 3a35120a77ec0ceb814a1cdcacff32fef32b4f7b..25717bc9be98824e38f3c27c3299fbd1f2e7e299 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
> @@ -18,6 +18,7 @@ properties:
>      enum:
>        - qcom,glymur-qmp-gen4x2-pcie-phy
>        - qcom,glymur-qmp-gen5x4-pcie-phy
> +      - qcom,glymur-qmp-gen5x8-pcie-phy
>        - qcom,kaanapali-qmp-gen3x2-pcie-phy
>        - qcom,qcs615-qmp-gen3x1-pcie-phy
>        - qcom,qcs8300-qmp-gen4x2-pcie-phy
> @@ -68,20 +69,23 @@ properties:
>        - const: ref
>        - enum: [rchng, refgen]
>        - const: pipe
> -      - const: pipediv2
> +      - enum: [phy_b_aux, pipediv2]
>  
>    power-domains:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 2

Once there is more than 1, you have to define the order and what each 
one is for.

>  
>    resets:
>      minItems: 1
> -    maxItems: 2
> +    maxItems: 4
>  
>    reset-names:
>      minItems: 1
>      items:
>        - const: phy
>        - const: phy_nocsr
> +      - const: phy_b
> +      - const: phy_b_nocsr
>  
>    vdda-phy-supply: true
>  
> @@ -183,6 +187,7 @@ allOf:
>              enum:
>                - qcom,glymur-qmp-gen4x2-pcie-phy
>                - qcom,glymur-qmp-gen5x4-pcie-phy
> +              - qcom,glymur-qmp-gen5x8-pcie-phy
>                - qcom,qcs8300-qmp-gen4x2-pcie-phy
>                - qcom,sa8775p-qmp-gen4x2-pcie-phy
>                - qcom,sa8775p-qmp-gen4x4-pcie-phy
> @@ -201,6 +206,17 @@ allOf:
>          clock-names:
>            minItems: 6
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,glymur-qmp-gen5x8-pcie-phy
> +    then:
> +      properties:
> +        power-domains:
> +          minItems: 2

else:
  maxItems: 1

> +
>    - if:
>        properties:
>          compatible:
> @@ -223,11 +239,24 @@ allOf:
>          reset-names:
>            minItems: 2
>      else:
> -      properties:
> -        resets:
> -          maxItems: 1
> -        reset-names:
> -          maxItems: 1
> +      if:
> +        properties:
> +          compatible:
> +            contains:
> +              enum:
> +                - qcom,glymur-qmp-gen5x8-pcie-phy
> +      then:
> +        properties:
> +          resets:
> +            minItems: 4
> +          reset-names:
> +            minItems: 4
> +      else:
> +        properties:
> +          resets:
> +            maxItems: 1
> +          reset-names:
> +            maxItems: 1
>  
>    - if:
>        properties:
> 
> -- 
> 2.34.1
> 

  reply	other threads:[~2026-04-07 16:13 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-23  7:15 [PATCH v2 0/5] phy: qcom: qmp-pcie: Add PCIe Gen5 8-lane bifurcation support for Glymur Qiang Yu
2026-03-23  7:15 ` [PATCH v2 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add support for glymur Gen5 x8 bifurcation mode Qiang Yu
2026-04-07 16:13   ` Rob Herring [this message]
2026-03-23  7:15 ` [PATCH v2 2/5] phy: qcom: qmp-pcie: Add multiple power-domains support Qiang Yu
2026-03-24 21:18   ` Dmitry Baryshkov
2026-03-23  7:15 ` [PATCH v2 3/5] phy: qcom: qmp-pcie: Support multiple nocsr resets Qiang Yu
2026-03-23  7:15 ` [PATCH v2 4/5] phy: qcom: qmp-pcie: Add Gen5 8-lanes mode for Glymur Qiang Yu
2026-03-24 16:26   ` Abel Vesa
2026-03-24 21:23   ` Dmitry Baryshkov
2026-03-31  9:59     ` Qiang Yu
2026-04-01 14:08       ` Dmitry Baryshkov
2026-04-01 14:41       ` Bjorn Andersson
2026-04-07  1:49         ` Qiang Yu
2026-03-23  7:15 ` [PATCH v2 5/5] arch: arm64: dts: qcom: Add support for PCIe3a Qiang Yu
2026-03-24 21:21   ` Dmitry Baryshkov
2026-03-31 10:00     ` Qiang Yu

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