From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8F033ACA4C for ; Wed, 8 Apr 2026 10:32:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.169 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775644337; cv=none; b=u68AQoUhwG/oHMAtlwY774rGdAVCAux+gWl4n0i0GORhP3fKhU904NZw9Qex7SUMsZhYvEtg/DGvSk04dmHzdgVk9Teu7R9QGh8JTrN9TwBYQ5U8htAlju05sJNhIDDXPUxERMwbRzoPtaz+EHwazNeYf3Rv69ar2huzP/XjKnc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775644337; c=relaxed/simple; bh=a+37Q96AQf19bRYbXYxBQBrSVvXfyJnYaGeOZD4E6hY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=USF4IyI+0lgHYsytGKEZymVUFXcvTWw7KZJa+ZQAa6j3t7CnBKlgf4GzHhyRgJLcGfqhOX2MC4a+s49lhSWIF9gOc56z+zqL/ThNms8X9exq7SQIQnkX2LKHeaZYGatr1Bt3bf+xC0DZW3aB5IdwG0eh5LTl5aMnC6LCfvvdObE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=PnyjqR6m; arc=none smtp.client-ip=209.85.210.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PnyjqR6m" Received: by mail-pf1-f169.google.com with SMTP id d2e1a72fcca58-82d561b3689so683573b3a.0 for ; Wed, 08 Apr 2026 03:32:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1775644333; x=1776249133; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BUmSeMeQCUmRExPRZysU8P/gIvmGNcoeaZ6w3DzGjQM=; b=PnyjqR6mJ/HnBUH+Lupnh5SjJc4tVWM7Es6llx2L/tYEs+dLB9BDqCejBnQiS1ufHE aiDP1gvbRKLOj6hbdDTJ9SrNDZJKCYq4WBquL61AO5gg+5YOMBOImXWzhNEkpTDgR0Xr xRMy670Az5LPxWlIOLFKY+7LR+IU9dvi49Crhf0oAvr8GNmh/GPEpasX5EEJNJOgKTlN uT7fzD2HGb8LKm/a9X/bes0RBogj4LcidaB/rf/p0zWQJ539URSArYu3tWq1l1S4yhyH /Kw/temGc31zXnqCdeQRQpP8cml6pOyKqDwD4J8vJ1ccj+WWZ71W29lXmojbcVhBYKRT y6Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775644333; x=1776249133; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=BUmSeMeQCUmRExPRZysU8P/gIvmGNcoeaZ6w3DzGjQM=; b=K7J7Nupva8FuvP2/njMAhf4x2jYKXfWN0OVCOTN6j9JBG5uwsPTUPXrvBshU7rzPv4 VFYgrddKSqPY1h1XnVf0hLfYoPpkOTeBK7anT8D+aJs1lraKuyPeqd8HFkmUrGhttbsJ W2+IXksWo9QcB+0Fnjm+dvHqKo7UH2STXNbJr7SFYelBMCs9aK2fve8ciH9CpzSR0ee+ GsszYt+LSjbTHn4nZHjwKovkqPzfyy6dMMNo0Ec7anmNBRZ4psW790N8r5l0+4bv3taw nvPse4mcdgbnIJ6p46L3IMUS+XSpzlyFpwiJBx35gjnJIcm1+Dlv/zVDgaaaigB4dmPl OrWA== X-Forwarded-Encrypted: i=1; AJvYcCUXuzQveAp+zURYckxtY+cW/DEhKl8zOsF93zEnQFI0c5Eo/vDqdI3CSxAwWvlXJxUQ0AwsHSwgdRqy8Aw=@vger.kernel.org X-Gm-Message-State: AOJu0YzdfQdBhonXvP2kFwwQZidv6woUkfWSqTGb84WBqdR+U3dmrTNb Eo914PzJeY337zeZiOifFI5i9XBxdtR9poJO8KTju0XS0OaUH2mDFQgF X-Gm-Gg: AeBDies1dhVK1sFhlbjFSyFRQLyE0mP8Pd7Ut9yPjzmff0/iVInYzSSJFZJZ1HFyBs0 pgp/pPC7vg+jT7DFX5FEumtC2mJikZP+EqgngG9ucCDDCpv2yaab/MtNn5ay6mddin+JIyMbUE1 2tZFlzAXC2qf6bSxvia3papmepM33mMu1EF0OeLUuymHXk/FLVkhb3ZV1qMGc02Fr30vpqYc8F4 6uR90i/EPJ3xquYZP4aUVZHIrMuvlZfLVn8ejabgQ749DWro5LR8zHmmwdxa0AteGMjp8FkE/kk aCx+Wy44XbSlMIPYroZAWkLHI/EJ6COGy8uO2PNAqcp85VUr79Xxz2Iv4j5+mVo3apbog+W5F0C 4R2FEu5heBo0JgHSqTehNAm7usyr7mBHGkIyonO3/74DCkPS4838pjhteF1XMMFRud7HN2DJjLZ y4kjb4KABtoMNacZE7XVNb5Egk4uLAC9c2T1oEWr3J2D5bX1dndvQ0og== X-Received: by 2002:a05:6a00:1d95:b0:81f:1a4b:bf50 with SMTP id d2e1a72fcca58-82d0db71e39mr20315977b3a.36.1775644332759; Wed, 08 Apr 2026 03:32:12 -0700 (PDT) Received: from localhost (as040201.dynamic.ppp.asahi-net.or.jp. [150.9.40.201]) by smtp.gmail.com with UTF8SMTPSA id d2e1a72fcca58-82cf9ca14b3sm23344993b3a.54.2026.04.08.03.32.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Apr 2026 03:32:12 -0700 (PDT) From: osjin83@gmail.com To: Greg Kroah-Hartman Cc: linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org, osjin83@gmail.com Subject: [PATCH 1/3] staging: rtl8723bs: fix spacing around operators in rtl8723b_phycfg.c Date: Wed, 8 Apr 2026 19:32:06 +0900 Message-ID: <20260408103208.7682-2-osjin83@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260408103208.7682-1-osjin83@gmail.com> References: <20260408103208.7682-1-osjin83@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: tas0dev Fix various spacing issues reported by checkpatch.pl to improve code readability and conform to the Linux kernel coding style. Specifically, this patch: - Adds missing spaces around binary operators (| , >> , << , + , &). - Corrects the spacing in bitwise expressions within function calls. - Ensures consistent use of whitespace in arithmetic operations. These changes are purely cosmetic and do not alter the functional behavior of the driver. Signed-off-by: tas0dev --- .../staging/rtl8723bs/hal/rtl8723b_phycfg.c | 44 +++++++++---------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c index 7fac1c2ba8e0..cfa00775341b 100644 --- a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c +++ b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c @@ -19,7 +19,7 @@ static u32 phy_CalculateBitShift(u32 BitMask) u32 i; for (i = 0; i <= 31; i++) { - if (((BitMask>>i) & 0x1) == 1) + if (((BitMask >> i) & 0x1) == 1) break; } return i; @@ -109,18 +109,18 @@ static u32 phy_RFSerialRead_8723B( NewOffset = Offset; if (eRFPath == RF_PATH_A) { - tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord); - tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; /* T65 RF */ - PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge)); + tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord); + tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /* T65 RF */ + PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge)); } else { - tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord); - tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; /* T65 RF */ - PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge)); + tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord); + tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /* T65 RF */ + PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge)); } - tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord); - PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge)); - PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge); + tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord); + PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge)); + PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge); udelay(10); @@ -129,16 +129,16 @@ static u32 phy_RFSerialRead_8723B( udelay(10); if (eRFPath == RF_PATH_A) - RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8); + RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1 | MaskforPhySet, BIT8); else if (eRFPath == RF_PATH_B) - RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1|MaskforPhySet, BIT8); + RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1 | MaskforPhySet, BIT8); if (RfPiEnable) { /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */ - retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi|MaskforPhySet, bLSSIReadBackData); + retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi | MaskforPhySet, bLSSIReadBackData); } else { /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */ - retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack|MaskforPhySet, bLSSIReadBackData); + retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack | MaskforPhySet, bLSSIReadBackData); } return retValue; @@ -203,7 +203,7 @@ static void phy_RFSerialWrite_8723B( /* */ /* Put write addr in [5:0] and write data in [31:16] */ /* */ - DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; /* T65 RF */ + DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff; /* T65 RF */ /* */ /* Write Operation */ /* */ @@ -266,7 +266,7 @@ void PHY_SetRFReg_8723B( if (BitMask != bRFRegOffsetMask) { Original_Value = phy_RFSerialRead_8723B(Adapter, eRFPath, RegAddr); BitShift = phy_CalculateBitShift(BitMask); - Data = ((Original_Value & (~BitMask)) | (Data<nCur40MhzPrimeSC>>1)); + PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1)); PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC); - PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); + PHY_SetBBReg(Adapter, 0x818, (BIT26 | BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); break; default: break; -- 2.53.0