From: Bjorn Helgaas <helgaas@kernel.org>
To: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Cc: bhelgaas@google.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org,
thierry.reding@gmail.com, jonathanh@nvidia.com,
kishon@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org,
Frank.Li@nxp.com, den@valinux.co.jp, hongxing.zhu@nxp.com,
jingoohan1@gmail.com, vidyas@nvidia.com, cassel@kernel.org,
18255117159@163.com, linux-pci@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v8 9/9] PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency
Date: Wed, 8 Apr 2026 17:30:27 -0500 [thread overview]
Message-ID: <20260408223027.GA371101@bhelgaas> (raw)
In-Reply-To: <20260324191000.1095768-10-mmaddireddy@nvidia.com>
On Wed, Mar 25, 2026 at 12:40:00AM +0530, Manikanta Maddireddy wrote:
> Program ASPM L1 entrance latency from the optional aspm-l1-entry-delay-ns
> device tree property instead of of_data. Convert the value from nanoseconds
> to the hardware encoding (log2(us) + 1, 3-bit field). If the property is
> absent, default to 7 (maximum latency).
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V8: Use aspm-l1-entry-delay-ns instead of of_data
> Changes V1 -> V7: None
>
> drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 3278353b2c29..a856a48362df 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -18,6 +18,7 @@
> #include <linux/interrupt.h>
> #include <linux/iopoll.h>
> #include <linux/kernel.h>
> +#include <linux/log2.h>
> #include <linux/module.h>
> #include <linux/of.h>
> #include <linux/of_pci.h>
> @@ -272,6 +273,7 @@ struct tegra_pcie_dw {
> u32 aspm_cmrt;
> u32 aspm_pwr_on_t;
> u32 aspm_l0s_enter_lat;
> + u32 aspm_l1_enter_lat;
>
> struct regulator *pex_ctl_supply;
> struct regulator *slot_ctl_3v3;
> @@ -710,6 +712,8 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
> val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
> val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
> val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
> + val &= ~PORT_AFR_L1_ENTRANCE_LAT_MASK;
> + val |= (pcie->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT);
> val |= PORT_AFR_ENTER_ASPM;
> dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
> }
> @@ -1110,6 +1114,7 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
> {
> struct platform_device *pdev = to_platform_device(pcie->dev);
> struct device_node *np = pcie->dev->of_node;
> + u32 val;
> int ret;
>
> pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
> @@ -1136,6 +1141,15 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
> dev_info(pcie->dev,
> "Failed to read ASPM L0s Entrance latency: %d\n", ret);
>
> + /* Default to max latency of 7. */
> + pcie->aspm_l1_enter_lat = 7;
> + ret = of_property_read_u32(np, "aspm-l1-entry-delay-ns", &val);
> + if (!ret) {
> + u32 us = max(val / 1000, 1U);
> +
> + pcie->aspm_l1_enter_lat = min(ilog2(us) + 1, 7U);
I haven't investigated yet, but I see this build error on
pci/controller/dwc-tegra194:
CC drivers/pci/controller/dwc/pcie-tegra194.o
In file included from <command-line>:
In function ‘tegra_pcie_dw_parse_dt’,
inlined from ‘tegra_pcie_dw_probe’ at drivers/pci/controller/dwc/pcie-tegra194.c:2148:8:
././include/linux/compiler_types.h:706:45: error: call to ‘__compiletime_assert_515’ declared with attribute error: min(( __builtin_constant_p(us) ? ((us) < 2 ? 0 : 63 - __builtin_clzll(us)) : (sizeof(us) <= 4) ? __ilog2_u32(us) : __ilog2_u64(us) ) + 1, 7U) signedness error
706 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^
././include/linux/compiler_types.h:687:25: note: in definition of macro ‘__compiletime_assert’
687 | prefix ## suffix(); \
| ^~~~~~
././include/linux/compiler_types.h:706:9: note: in expansion of macro ‘_compiletime_assert’
706 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
./include/linux/minmax.h:93:9: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
93 | BUILD_BUG_ON_MSG(!__types_ok(ux, uy), \
| ^~~~~~~~~~~~~~~~
./include/linux/minmax.h:98:9: note: in expansion of macro ‘__careful_cmp_once’
98 | __careful_cmp_once(op, x, y, __UNIQUE_ID(x_), __UNIQUE_ID(y_))
| ^~~~~~~~~~~~~~~~~~
./include/linux/minmax.h:105:25: note: in expansion of macro ‘__careful_cmp’
105 | #define min(x, y) __careful_cmp(min, x, y)
| ^~~~~~~~~~~~~
drivers/pci/controller/dwc/pcie-tegra194.c:1155:43: note: in expansion of macro ‘min’
1155 | pcie->aspm_l1_enter_lat = min(ilog2(us) + 1, 7U);
| ^~~
next prev parent reply other threads:[~2026-04-08 22:30 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-24 19:09 [PATCH v8 0/9] Enhancements to pcie-tegra194 driver Manikanta Maddireddy
2026-03-24 19:09 ` [PATCH v8 1/9] PCI: tegra194: Drive CLKREQ# signal low explicitly Manikanta Maddireddy
2026-03-24 19:09 ` [PATCH v8 2/9] PCI: tegra194: Calibrate pipe to UPHY for Endpoint mode Manikanta Maddireddy
2026-03-24 19:09 ` [PATCH v8 3/9] PCI: tegra194: Remove IRQF_ONESHOT flag during Endpoint interrupt registration Manikanta Maddireddy
2026-03-24 19:09 ` [PATCH v8 4/9] PCI: tegra194: Enable DMA interrupt Manikanta Maddireddy
2026-03-24 19:09 ` [PATCH v8 5/9] PCI: tegra194: Enable hardware hot reset mode in Endpoint Manikanta Maddireddy
2026-03-24 19:09 ` [PATCH v8 6/9] dt-bindings: PCI: tegra194: Add monitor clock support Manikanta Maddireddy
2026-03-24 19:09 ` [PATCH v8 7/9] PCI: tegra194: Add core " Manikanta Maddireddy
2026-03-24 19:09 ` [PATCH v8 8/9] arm64: tegra: Add aspm-l1-entry-delay-ns to PCIe nodes Manikanta Maddireddy
2026-03-24 19:10 ` [PATCH v8 9/9] PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency Manikanta Maddireddy
2026-04-08 22:30 ` Bjorn Helgaas [this message]
2026-04-09 5:56 ` Manikanta Maddireddy
2026-04-09 18:40 ` Bjorn Helgaas
2026-04-09 18:36 ` Bjorn Helgaas
2026-04-04 15:28 ` (subset) [PATCH v8 0/9] Enhancements to pcie-tegra194 driver Manivannan Sadhasivam
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