From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CED63E123C for ; Fri, 10 Apr 2026 18:08:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775844511; cv=none; b=Hv3ISkEIP4ZoKcprlII1drt59HsbAKxbnkPEhBEbtZUO3B+GK7fM4WEl5IVN4G6FIPb756KYzJg9rxe8wc9eyEjbqalN0Swx8rZ/andd9yBhN5mPH+kl4cqdo2obca5zoYVxHrtPoh+l3HMQQA4Lk7UX2mdLVZEJ3WgzO87sP90= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775844511; c=relaxed/simple; bh=y3LM0sU4axh6UrJQBefLWitalJFNSzQ3niKQlSuqcVU=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dPjfUue37FQ781mT+IMlnLuk4/yZT7Y9QIngU850iKGGmtJisqbUub7/gWgBfYpZb5iMgpXelSbb2XXU/tZJPj0BgUiyAXCcgC6VoKSnF5IDASWHMbDFbXjTXorq4pPlRLnT1yVvWlT2BoaPMXMGKdswjlKgjNhkzIKHV7iUd0g= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=azJ9ohxC; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="azJ9ohxC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1775844508; bh=y3LM0sU4axh6UrJQBefLWitalJFNSzQ3niKQlSuqcVU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=azJ9ohxCNNLlGqAmRNHgBkRDKKeQEg5dzcofW+N+jQYa67OBVVRQ9NKQFG/7qAHbE 7CeUGfDZ5xp+eldnLpZ22ycKp0DK+VO+PBsVzL3ongr6x3qiAnPooXUVN0LJgIXOLh 8rCrLz1cMrqNAfY9TYacsi0pIu9rUJpgRLjzPG8WzkyzunYl32BMM5ucicWaXw9T1k N9u6yrZsOAIHs8cUrDYwCi0qRclw21Q2t4dnbZhFta77P82/GcIGVFWKonlbmW7vgH g+nSesfoH6pqXbJocFEqcoVy3pTB7cw2Gf6ntpFsjqe8PZWbg8BhD2yvTJr9/p27MA 3hR54j6lkPIUw== Received: from fedora (unknown [100.64.0.11]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbrezillon) by bali.collaboradmins.com (Postfix) with ESMTPSA id DAEB617E05FC; Fri, 10 Apr 2026 20:08:27 +0200 (CEST) Date: Fri, 10 Apr 2026 20:08:23 +0200 From: Boris Brezillon To: Karunika Choo Cc: dri-devel@lists.freedesktop.org, nd@arm.com, Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/8] drm/panthor: Split register definitions by components Message-ID: <20260410200823.5110f2b6@fedora> In-Reply-To: <20260410164637.549145-3-karunika.choo@arm.com> References: <20260410164637.549145-1-karunika.choo@arm.com> <20260410164637.549145-3-karunika.choo@arm.com> Organization: Collabora X-Mailer: Claws Mail 4.3.1 (GTK 3.24.51; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Fri, 10 Apr 2026 17:46:31 +0100 Karunika Choo wrote: > --- /dev/null > +++ b/drivers/gpu/drm/panthor/panthor_hw_regs.h > @@ -0,0 +1,16 @@ > +/* SPDX-License-Identifier: GPL-2.0 or MIT */ > +/* Copyright 2026 ARM Limited. All rights reserved. */ > + > +#ifndef __PANTHOR_HW_REGS_H__ > +#define __PANTHOR_HW_REGS_H__ > + > +#define GPU_ID 0x0 > +#define GPU_ARCH_MAJOR(x) ((x) >> 28) > +#define GPU_ARCH_MINOR(x) (((x) & GENMASK(27, 24)) >> 24) > +#define GPU_ARCH_REV(x) (((x) & GENMASK(23, 20)) >> 20) > +#define GPU_PROD_MAJOR(x) (((x) & GENMASK(19, 16)) >> 16) > +#define GPU_VER_MAJOR(x) (((x) & GENMASK(15, 12)) >> 12) > +#define GPU_VER_MINOR(x) (((x) & GENMASK(11, 4)) >> 4) > +#define GPU_VER_STATUS(x) ((x) & GENMASK(3, 0)) Any particular reason for not having those defined in panthor_gpu_regs.h? > + > +#endif /* __PANTHOR_HW_REGS_H__ */