* [PATCH 1/8] drm/panthor: Pass an iomem pointer to GPU register access helpers
2026-04-10 16:46 [PATCH 0/8] drm/panthor: Localize register access by component Karunika Choo
@ 2026-04-10 16:46 ` Karunika Choo
2026-04-10 18:11 ` Boris Brezillon
2026-04-10 16:46 ` [PATCH 2/8] drm/panthor: Split register definitions by components Karunika Choo
` (6 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Karunika Choo @ 2026-04-10 16:46 UTC (permalink / raw)
To: dri-devel
Cc: nd, Boris Brezillon, Steven Price, Liviu Dudau, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
linux-kernel
Convert the Panthor register access helpers to take an iomem pointer
instead of a panthor_device pointer.
This makes the helpers usable with block-local registers instead of
routing all accesses to go through ptdev->iomem. It is a preparatory
change for splitting the register space by components and for moving
callers away from cross-component register accesses.
No functional change intended.
Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
drivers/gpu/drm/panthor/panthor_device.c | 2 +-
drivers/gpu/drm/panthor/panthor_device.h | 78 ++++++++++++------------
drivers/gpu/drm/panthor/panthor_drv.c | 6 +-
drivers/gpu/drm/panthor/panthor_fw.c | 22 +++----
drivers/gpu/drm/panthor/panthor_gpu.c | 42 ++++++-------
drivers/gpu/drm/panthor/panthor_hw.c | 47 +++++++-------
drivers/gpu/drm/panthor/panthor_mmu.c | 29 +++++----
drivers/gpu/drm/panthor/panthor_pwr.c | 61 +++++++++---------
drivers/gpu/drm/panthor/panthor_sched.c | 2 +-
9 files changed, 146 insertions(+), 143 deletions(-)
diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/panthor/panthor_device.c
index bc62a498a8a8..d62017b73409 100644
--- a/drivers/gpu/drm/panthor/panthor_device.c
+++ b/drivers/gpu/drm/panthor/panthor_device.c
@@ -43,7 +43,7 @@ static int panthor_gpu_coherency_init(struct panthor_device *ptdev)
/* Check if the ACE-Lite coherency protocol is actually supported by the GPU.
* ACE protocol has never been supported for command stream frontend GPUs.
*/
- if ((gpu_read(ptdev, GPU_COHERENCY_FEATURES) &
+ if ((gpu_read(ptdev->iomem, GPU_COHERENCY_FEATURES) &
GPU_COHERENCY_PROT_BIT(ACE_LITE))) {
ptdev->gpu_info.selected_coherency = GPU_COHERENCY_ACE_LITE;
return 0;
diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/panthor/panthor_device.h
index 5cba272f9b4d..285bf7e4439e 100644
--- a/drivers/gpu/drm/panthor/panthor_device.h
+++ b/drivers/gpu/drm/panthor/panthor_device.h
@@ -505,7 +505,7 @@ static irqreturn_t panthor_ ## __name ## _irq_raw_handler(int irq, void *data)
struct panthor_device *ptdev = pirq->ptdev; \
enum panthor_irq_state old_state; \
\
- if (!gpu_read(ptdev, __reg_prefix ## _INT_STAT)) \
+ if (!gpu_read(ptdev->iomem, __reg_prefix ## _INT_STAT)) \
return IRQ_NONE; \
\
guard(spinlock_irqsave)(&pirq->mask_lock); \
@@ -515,7 +515,7 @@ static irqreturn_t panthor_ ## __name ## _irq_raw_handler(int irq, void *data)
if (old_state != PANTHOR_IRQ_STATE_ACTIVE) \
return IRQ_NONE; \
\
- gpu_write(ptdev, __reg_prefix ## _INT_MASK, 0); \
+ gpu_write(ptdev->iomem, __reg_prefix ## _INT_MASK, 0); \
return IRQ_WAKE_THREAD; \
} \
\
@@ -534,7 +534,7 @@ static irqreturn_t panthor_ ## __name ## _irq_threaded_handler(int irq, void *da
* right before the HW event kicks in. TLDR; it's all expected races we're \
* covered for. \
*/ \
- u32 status = gpu_read(ptdev, __reg_prefix ## _INT_RAWSTAT) & pirq->mask; \
+ u32 status = gpu_read(ptdev->iomem, __reg_prefix ## _INT_RAWSTAT) & pirq->mask; \
\
if (!status) \
break; \
@@ -550,7 +550,7 @@ static irqreturn_t panthor_ ## __name ## _irq_threaded_handler(int irq, void *da
PANTHOR_IRQ_STATE_PROCESSING, \
PANTHOR_IRQ_STATE_ACTIVE); \
if (old_state == PANTHOR_IRQ_STATE_PROCESSING) \
- gpu_write(ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \
+ gpu_write(ptdev->iomem, __reg_prefix ## _INT_MASK, pirq->mask); \
} \
\
return ret; \
@@ -560,7 +560,7 @@ static inline void panthor_ ## __name ## _irq_suspend(struct panthor_irq *pirq)
{ \
scoped_guard(spinlock_irqsave, &pirq->mask_lock) { \
atomic_set(&pirq->state, PANTHOR_IRQ_STATE_SUSPENDING); \
- gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, 0); \
+ gpu_write(pirq->ptdev->iomem, __reg_prefix ## _INT_MASK, 0); \
} \
synchronize_irq(pirq->irq); \
atomic_set(&pirq->state, PANTHOR_IRQ_STATE_SUSPENDED); \
@@ -571,8 +571,8 @@ static inline void panthor_ ## __name ## _irq_resume(struct panthor_irq *pirq)
guard(spinlock_irqsave)(&pirq->mask_lock); \
\
atomic_set(&pirq->state, PANTHOR_IRQ_STATE_ACTIVE); \
- gpu_write(pirq->ptdev, __reg_prefix ## _INT_CLEAR, pirq->mask); \
- gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \
+ gpu_write(pirq->ptdev->iomem, __reg_prefix ## _INT_CLEAR, pirq->mask); \
+ gpu_write(pirq->ptdev->iomem, __reg_prefix ## _INT_MASK, pirq->mask); \
} \
\
static int panthor_request_ ## __name ## _irq(struct panthor_device *ptdev, \
@@ -603,7 +603,7 @@ static inline void panthor_ ## __name ## _irq_enable_events(struct panthor_irq *
* If the IRQ is suspended/suspending, the mask is restored at resume time. \
*/ \
if (atomic_read(&pirq->state) == PANTHOR_IRQ_STATE_ACTIVE) \
- gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \
+ gpu_write(pirq->ptdev->iomem, __reg_prefix ## _INT_MASK, pirq->mask); \
} \
\
static inline void panthor_ ## __name ## _irq_disable_events(struct panthor_irq *pirq, u32 mask)\
@@ -617,80 +617,80 @@ static inline void panthor_ ## __name ## _irq_disable_events(struct panthor_irq
* If the IRQ is suspended/suspending, the mask is restored at resume time. \
*/ \
if (atomic_read(&pirq->state) == PANTHOR_IRQ_STATE_ACTIVE) \
- gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \
+ gpu_write(pirq->ptdev->iomem, __reg_prefix ## _INT_MASK, pirq->mask); \
}
extern struct workqueue_struct *panthor_cleanup_wq;
-static inline void gpu_write(struct panthor_device *ptdev, u32 reg, u32 data)
+static inline void gpu_write(void __iomem *iomem, u32 reg, u32 data)
{
- writel(data, ptdev->iomem + reg);
+ writel(data, iomem + reg);
}
-static inline u32 gpu_read(struct panthor_device *ptdev, u32 reg)
+static inline u32 gpu_read(void __iomem *iomem, u32 reg)
{
- return readl(ptdev->iomem + reg);
+ return readl(iomem + reg);
}
-static inline u32 gpu_read_relaxed(struct panthor_device *ptdev, u32 reg)
+static inline u32 gpu_read_relaxed(void __iomem *iomem, u32 reg)
{
- return readl_relaxed(ptdev->iomem + reg);
+ return readl_relaxed(iomem + reg);
}
-static inline void gpu_write64(struct panthor_device *ptdev, u32 reg, u64 data)
+static inline void gpu_write64(void __iomem *iomem, u32 reg, u64 data)
{
- gpu_write(ptdev, reg, lower_32_bits(data));
- gpu_write(ptdev, reg + 4, upper_32_bits(data));
+ gpu_write(iomem, reg, lower_32_bits(data));
+ gpu_write(iomem, reg + 4, upper_32_bits(data));
}
-static inline u64 gpu_read64(struct panthor_device *ptdev, u32 reg)
+static inline u64 gpu_read64(void __iomem *iomem, u32 reg)
{
- return (gpu_read(ptdev, reg) | ((u64)gpu_read(ptdev, reg + 4) << 32));
+ return (gpu_read(iomem, reg) | ((u64)gpu_read(iomem, reg + 4) << 32));
}
-static inline u64 gpu_read64_relaxed(struct panthor_device *ptdev, u32 reg)
+static inline u64 gpu_read64_relaxed(void __iomem *iomem, u32 reg)
{
- return (gpu_read_relaxed(ptdev, reg) |
- ((u64)gpu_read_relaxed(ptdev, reg + 4) << 32));
+ return (gpu_read_relaxed(iomem, reg) |
+ ((u64)gpu_read_relaxed(iomem, reg + 4) << 32));
}
-static inline u64 gpu_read64_counter(struct panthor_device *ptdev, u32 reg)
+static inline u64 gpu_read64_counter(void __iomem *iomem, u32 reg)
{
u32 lo, hi1, hi2;
do {
- hi1 = gpu_read(ptdev, reg + 4);
- lo = gpu_read(ptdev, reg);
- hi2 = gpu_read(ptdev, reg + 4);
+ hi1 = gpu_read(iomem, reg + 4);
+ lo = gpu_read(iomem, reg);
+ hi2 = gpu_read(iomem, reg + 4);
} while (hi1 != hi2);
return lo | ((u64)hi2 << 32);
}
-#define gpu_read_poll_timeout(dev, reg, val, cond, delay_us, timeout_us) \
+#define gpu_read_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us) \
read_poll_timeout(gpu_read, val, cond, delay_us, timeout_us, false, \
- dev, reg)
+ iomem, reg)
-#define gpu_read_poll_timeout_atomic(dev, reg, val, cond, delay_us, \
+#define gpu_read_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \
timeout_us) \
read_poll_timeout_atomic(gpu_read, val, cond, delay_us, timeout_us, \
- false, dev, reg)
+ false, iomem, reg)
-#define gpu_read64_poll_timeout(dev, reg, val, cond, delay_us, timeout_us) \
+#define gpu_read64_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us) \
read_poll_timeout(gpu_read64, val, cond, delay_us, timeout_us, false, \
- dev, reg)
+ iomem, reg)
-#define gpu_read64_poll_timeout_atomic(dev, reg, val, cond, delay_us, \
+#define gpu_read64_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \
timeout_us) \
read_poll_timeout_atomic(gpu_read64, val, cond, delay_us, timeout_us, \
- false, dev, reg)
+ false, iomem, reg)
-#define gpu_read_relaxed_poll_timeout_atomic(dev, reg, val, cond, delay_us, \
+#define gpu_read_relaxed_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \
timeout_us) \
read_poll_timeout_atomic(gpu_read_relaxed, val, cond, delay_us, \
- timeout_us, false, dev, reg)
+ timeout_us, false, iomem, reg)
-#define gpu_read64_relaxed_poll_timeout(dev, reg, val, cond, delay_us, \
+#define gpu_read64_relaxed_poll_timeout(iomem, reg, val, cond, delay_us, \
timeout_us) \
read_poll_timeout(gpu_read64_relaxed, val, cond, delay_us, timeout_us, \
- false, dev, reg)
+ false, iomem, reg)
#endif
diff --git a/drivers/gpu/drm/panthor/panthor_drv.c b/drivers/gpu/drm/panthor/panthor_drv.c
index 73fc983dc9b4..4f926c861fba 100644
--- a/drivers/gpu/drm/panthor/panthor_drv.c
+++ b/drivers/gpu/drm/panthor/panthor_drv.c
@@ -839,7 +839,7 @@ static int panthor_query_timestamp_info(struct panthor_device *ptdev,
}
if (flags & DRM_PANTHOR_TIMESTAMP_GPU_OFFSET)
- arg->timestamp_offset = gpu_read64(ptdev, GPU_TIMESTAMP_OFFSET);
+ arg->timestamp_offset = gpu_read64(ptdev->iomem, GPU_TIMESTAMP_OFFSET);
else
arg->timestamp_offset = 0;
@@ -854,7 +854,7 @@ static int panthor_query_timestamp_info(struct panthor_device *ptdev,
query_start_time = 0;
if (flags & DRM_PANTHOR_TIMESTAMP_GPU)
- arg->current_timestamp = gpu_read64_counter(ptdev, GPU_TIMESTAMP);
+ arg->current_timestamp = gpu_read64_counter(ptdev->iomem, GPU_TIMESTAMP);
else
arg->current_timestamp = 0;
@@ -870,7 +870,7 @@ static int panthor_query_timestamp_info(struct panthor_device *ptdev,
}
if (flags & DRM_PANTHOR_TIMESTAMP_GPU_CYCLE_COUNT)
- arg->cycle_count = gpu_read64_counter(ptdev, GPU_CYCLE_COUNT);
+ arg->cycle_count = gpu_read64_counter(ptdev->iomem, GPU_CYCLE_COUNT);
else
arg->cycle_count = 0;
diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor/panthor_fw.c
index be0da5b1f3ab..69a19751a314 100644
--- a/drivers/gpu/drm/panthor/panthor_fw.c
+++ b/drivers/gpu/drm/panthor/panthor_fw.c
@@ -1054,7 +1054,7 @@ static void panthor_fw_init_global_iface(struct panthor_device *ptdev)
GLB_CFG_POWEROFF_TIMER |
GLB_CFG_PROGRESS_TIMER);
- gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
+ gpu_write(ptdev->iomem, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
/* Kick the watchdog. */
mod_delayed_work(ptdev->reset.wq, &ptdev->fw->watchdog.ping_work,
@@ -1069,7 +1069,7 @@ static void panthor_job_irq_handler(struct panthor_device *ptdev, u32 status)
if (tracepoint_enabled(gpu_job_irq))
start = ktime_get_ns();
- gpu_write(ptdev, JOB_INT_CLEAR, status);
+ gpu_write(ptdev->iomem, JOB_INT_CLEAR, status);
if (!ptdev->fw->booted && (status & JOB_INT_GLOBAL_IF))
ptdev->fw->booted = true;
@@ -1097,13 +1097,13 @@ static int panthor_fw_start(struct panthor_device *ptdev)
ptdev->fw->booted = false;
panthor_job_irq_enable_events(&ptdev->fw->irq, ~0);
panthor_job_irq_resume(&ptdev->fw->irq);
- gpu_write(ptdev, MCU_CONTROL, MCU_CONTROL_AUTO);
+ gpu_write(ptdev->iomem, MCU_CONTROL, MCU_CONTROL_AUTO);
if (!wait_event_timeout(ptdev->fw->req_waitqueue,
ptdev->fw->booted,
msecs_to_jiffies(1000))) {
if (!ptdev->fw->booted &&
- !(gpu_read(ptdev, JOB_INT_STAT) & JOB_INT_GLOBAL_IF))
+ !(gpu_read(ptdev->iomem, JOB_INT_STAT) & JOB_INT_GLOBAL_IF))
timedout = true;
}
@@ -1114,7 +1114,7 @@ static int panthor_fw_start(struct panthor_device *ptdev)
[MCU_STATUS_HALT] = "halt",
[MCU_STATUS_FATAL] = "fatal",
};
- u32 status = gpu_read(ptdev, MCU_STATUS);
+ u32 status = gpu_read(ptdev->iomem, MCU_STATUS);
drm_err(&ptdev->base, "Failed to boot MCU (status=%s)",
status < ARRAY_SIZE(status_str) ? status_str[status] : "unknown");
@@ -1128,8 +1128,8 @@ static void panthor_fw_stop(struct panthor_device *ptdev)
{
u32 status;
- gpu_write(ptdev, MCU_CONTROL, MCU_CONTROL_DISABLE);
- if (gpu_read_poll_timeout(ptdev, MCU_STATUS, status,
+ gpu_write(ptdev->iomem, MCU_CONTROL, MCU_CONTROL_DISABLE);
+ if (gpu_read_poll_timeout(ptdev->iomem, MCU_STATUS, status,
status == MCU_STATUS_DISABLED, 10, 100000))
drm_err(&ptdev->base, "Failed to stop MCU");
}
@@ -1139,7 +1139,7 @@ static bool panthor_fw_mcu_halted(struct panthor_device *ptdev)
struct panthor_fw_global_iface *glb_iface = panthor_fw_get_glb_iface(ptdev);
bool halted;
- halted = gpu_read(ptdev, MCU_STATUS) == MCU_STATUS_HALT;
+ halted = gpu_read(ptdev->iomem, MCU_STATUS) == MCU_STATUS_HALT;
if (panthor_fw_has_glb_state(ptdev))
halted &= (GLB_STATE_GET(glb_iface->output->ack) == GLB_STATE_HALT);
@@ -1156,7 +1156,7 @@ static void panthor_fw_halt_mcu(struct panthor_device *ptdev)
else
panthor_fw_update_reqs(glb_iface, req, GLB_HALT, GLB_HALT);
- gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
+ gpu_write(ptdev->iomem, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
}
static bool panthor_fw_wait_mcu_halted(struct panthor_device *ptdev)
@@ -1414,7 +1414,7 @@ void panthor_fw_ring_csg_doorbells(struct panthor_device *ptdev, u32 csg_mask)
struct panthor_fw_global_iface *glb_iface = panthor_fw_get_glb_iface(ptdev);
panthor_fw_toggle_reqs(glb_iface, doorbell_req, doorbell_ack, csg_mask);
- gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
+ gpu_write(ptdev->iomem, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
}
static void panthor_fw_ping_work(struct work_struct *work)
@@ -1429,7 +1429,7 @@ static void panthor_fw_ping_work(struct work_struct *work)
return;
panthor_fw_toggle_reqs(glb_iface, req, ack, GLB_PING);
- gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
+ gpu_write(ptdev->iomem, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
ret = panthor_fw_glb_wait_acks(ptdev, GLB_PING, &acked, 100);
if (ret) {
diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c
index 2ab444ee8c71..bdb72cebccb3 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu.c
+++ b/drivers/gpu/drm/panthor/panthor_gpu.c
@@ -56,7 +56,7 @@ struct panthor_gpu {
static void panthor_gpu_coherency_set(struct panthor_device *ptdev)
{
- gpu_write(ptdev, GPU_COHERENCY_PROTOCOL,
+ gpu_write(ptdev->iomem, GPU_COHERENCY_PROTOCOL,
ptdev->gpu_info.selected_coherency);
}
@@ -75,26 +75,26 @@ static void panthor_gpu_l2_config_set(struct panthor_device *ptdev)
}
for (i = 0; i < ARRAY_SIZE(data->asn_hash); i++)
- gpu_write(ptdev, GPU_ASN_HASH(i), data->asn_hash[i]);
+ gpu_write(ptdev->iomem, GPU_ASN_HASH(i), data->asn_hash[i]);
- l2_config = gpu_read(ptdev, GPU_L2_CONFIG);
+ l2_config = gpu_read(ptdev->iomem, GPU_L2_CONFIG);
l2_config |= GPU_L2_CONFIG_ASN_HASH_ENABLE;
- gpu_write(ptdev, GPU_L2_CONFIG, l2_config);
+ gpu_write(ptdev->iomem, GPU_L2_CONFIG, l2_config);
}
static void panthor_gpu_irq_handler(struct panthor_device *ptdev, u32 status)
{
- gpu_write(ptdev, GPU_INT_CLEAR, status);
+ gpu_write(ptdev->iomem, GPU_INT_CLEAR, status);
if (tracepoint_enabled(gpu_power_status) && (status & GPU_POWER_INTERRUPTS_MASK))
trace_gpu_power_status(ptdev->base.dev,
- gpu_read64(ptdev, SHADER_READY),
- gpu_read64(ptdev, TILER_READY),
- gpu_read64(ptdev, L2_READY));
+ gpu_read64(ptdev->iomem, SHADER_READY),
+ gpu_read64(ptdev->iomem, TILER_READY),
+ gpu_read64(ptdev->iomem, L2_READY));
if (status & GPU_IRQ_FAULT) {
- u32 fault_status = gpu_read(ptdev, GPU_FAULT_STATUS);
- u64 address = gpu_read64(ptdev, GPU_FAULT_ADDR);
+ u32 fault_status = gpu_read(ptdev->iomem, GPU_FAULT_STATUS);
+ u64 address = gpu_read64(ptdev->iomem, GPU_FAULT_ADDR);
drm_warn(&ptdev->base, "GPU Fault 0x%08x (%s) at 0x%016llx\n",
fault_status, panthor_exception_name(ptdev, fault_status & 0xFF),
@@ -204,7 +204,7 @@ int panthor_gpu_block_power_off(struct panthor_device *ptdev,
u32 val;
int ret;
- ret = gpu_read64_relaxed_poll_timeout(ptdev, pwrtrans_reg, val,
+ ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, pwrtrans_reg, val,
!(mask & val), 100, timeout_us);
if (ret) {
drm_err(&ptdev->base,
@@ -213,9 +213,9 @@ int panthor_gpu_block_power_off(struct panthor_device *ptdev,
return ret;
}
- gpu_write64(ptdev, pwroff_reg, mask);
+ gpu_write64(ptdev->iomem, pwroff_reg, mask);
- ret = gpu_read64_relaxed_poll_timeout(ptdev, pwrtrans_reg, val,
+ ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, pwrtrans_reg, val,
!(mask & val), 100, timeout_us);
if (ret) {
drm_err(&ptdev->base,
@@ -247,7 +247,7 @@ int panthor_gpu_block_power_on(struct panthor_device *ptdev,
u32 val;
int ret;
- ret = gpu_read64_relaxed_poll_timeout(ptdev, pwrtrans_reg, val,
+ ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, pwrtrans_reg, val,
!(mask & val), 100, timeout_us);
if (ret) {
drm_err(&ptdev->base,
@@ -256,9 +256,9 @@ int panthor_gpu_block_power_on(struct panthor_device *ptdev,
return ret;
}
- gpu_write64(ptdev, pwron_reg, mask);
+ gpu_write64(ptdev->iomem, pwron_reg, mask);
- ret = gpu_read64_relaxed_poll_timeout(ptdev, rdy_reg, val,
+ ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, rdy_reg, val,
(mask & val) == val,
100, timeout_us);
if (ret) {
@@ -326,7 +326,7 @@ int panthor_gpu_flush_caches(struct panthor_device *ptdev,
spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
if (!(ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED)) {
ptdev->gpu->pending_reqs |= GPU_IRQ_CLEAN_CACHES_COMPLETED;
- gpu_write(ptdev, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other));
+ gpu_write(ptdev->iomem, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other));
} else {
ret = -EIO;
}
@@ -340,7 +340,7 @@ int panthor_gpu_flush_caches(struct panthor_device *ptdev,
msecs_to_jiffies(100))) {
spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
if ((ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED) != 0 &&
- !(gpu_read(ptdev, GPU_INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED))
+ !(gpu_read(ptdev->iomem, GPU_INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED))
ret = -ETIMEDOUT;
else
ptdev->gpu->pending_reqs &= ~GPU_IRQ_CLEAN_CACHES_COMPLETED;
@@ -370,8 +370,8 @@ int panthor_gpu_soft_reset(struct panthor_device *ptdev)
if (!drm_WARN_ON(&ptdev->base,
ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED)) {
ptdev->gpu->pending_reqs |= GPU_IRQ_RESET_COMPLETED;
- gpu_write(ptdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED);
- gpu_write(ptdev, GPU_CMD, GPU_SOFT_RESET);
+ gpu_write(ptdev->iomem, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED);
+ gpu_write(ptdev->iomem, GPU_CMD, GPU_SOFT_RESET);
}
spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags);
@@ -380,7 +380,7 @@ int panthor_gpu_soft_reset(struct panthor_device *ptdev)
msecs_to_jiffies(100))) {
spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
if ((ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED) != 0 &&
- !(gpu_read(ptdev, GPU_INT_RAWSTAT) & GPU_IRQ_RESET_COMPLETED))
+ !(gpu_read(ptdev->iomem, GPU_INT_RAWSTAT) & GPU_IRQ_RESET_COMPLETED))
timedout = true;
else
ptdev->gpu->pending_reqs &= ~GPU_IRQ_RESET_COMPLETED;
diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor/panthor_hw.c
index d135aa6724fa..9309d0938212 100644
--- a/drivers/gpu/drm/panthor/panthor_hw.c
+++ b/drivers/gpu/drm/panthor/panthor_hw.c
@@ -194,35 +194,38 @@ static int panthor_gpu_info_init(struct panthor_device *ptdev)
{
unsigned int i;
- ptdev->gpu_info.csf_id = gpu_read(ptdev, GPU_CSF_ID);
- ptdev->gpu_info.gpu_rev = gpu_read(ptdev, GPU_REVID);
- ptdev->gpu_info.core_features = gpu_read(ptdev, GPU_CORE_FEATURES);
- ptdev->gpu_info.l2_features = gpu_read(ptdev, GPU_L2_FEATURES);
- ptdev->gpu_info.tiler_features = gpu_read(ptdev, GPU_TILER_FEATURES);
- ptdev->gpu_info.mem_features = gpu_read(ptdev, GPU_MEM_FEATURES);
- ptdev->gpu_info.mmu_features = gpu_read(ptdev, GPU_MMU_FEATURES);
- ptdev->gpu_info.thread_features = gpu_read(ptdev, GPU_THREAD_FEATURES);
- ptdev->gpu_info.max_threads = gpu_read(ptdev, GPU_THREAD_MAX_THREADS);
- ptdev->gpu_info.thread_max_workgroup_size = gpu_read(ptdev, GPU_THREAD_MAX_WORKGROUP_SIZE);
- ptdev->gpu_info.thread_max_barrier_size = gpu_read(ptdev, GPU_THREAD_MAX_BARRIER_SIZE);
- ptdev->gpu_info.coherency_features = gpu_read(ptdev, GPU_COHERENCY_FEATURES);
+ ptdev->gpu_info.csf_id = gpu_read(ptdev->iomem, GPU_CSF_ID);
+ ptdev->gpu_info.gpu_rev = gpu_read(ptdev->iomem, GPU_REVID);
+ ptdev->gpu_info.core_features = gpu_read(ptdev->iomem, GPU_CORE_FEATURES);
+ ptdev->gpu_info.l2_features = gpu_read(ptdev->iomem, GPU_L2_FEATURES);
+ ptdev->gpu_info.tiler_features = gpu_read(ptdev->iomem, GPU_TILER_FEATURES);
+ ptdev->gpu_info.mem_features = gpu_read(ptdev->iomem, GPU_MEM_FEATURES);
+ ptdev->gpu_info.mmu_features = gpu_read(ptdev->iomem, GPU_MMU_FEATURES);
+ ptdev->gpu_info.thread_features = gpu_read(ptdev->iomem, GPU_THREAD_FEATURES);
+ ptdev->gpu_info.max_threads = gpu_read(ptdev->iomem, GPU_THREAD_MAX_THREADS);
+ ptdev->gpu_info.thread_max_workgroup_size =
+ gpu_read(ptdev->iomem, GPU_THREAD_MAX_WORKGROUP_SIZE);
+ ptdev->gpu_info.thread_max_barrier_size =
+ gpu_read(ptdev->iomem, GPU_THREAD_MAX_BARRIER_SIZE);
+ ptdev->gpu_info.coherency_features = gpu_read(ptdev->iomem, GPU_COHERENCY_FEATURES);
for (i = 0; i < 4; i++)
- ptdev->gpu_info.texture_features[i] = gpu_read(ptdev, GPU_TEXTURE_FEATURES(i));
+ ptdev->gpu_info.texture_features[i] =
+ gpu_read(ptdev->iomem, GPU_TEXTURE_FEATURES(i));
- ptdev->gpu_info.as_present = gpu_read(ptdev, GPU_AS_PRESENT);
+ ptdev->gpu_info.as_present = gpu_read(ptdev->iomem, GPU_AS_PRESENT);
/* Introduced in arch 11.x */
- ptdev->gpu_info.gpu_features = gpu_read64(ptdev, GPU_FEATURES);
+ ptdev->gpu_info.gpu_features = gpu_read64(ptdev->iomem, GPU_FEATURES);
if (panthor_hw_has_pwr_ctrl(ptdev)) {
/* Introduced in arch 14.x */
- ptdev->gpu_info.l2_present = gpu_read64(ptdev, PWR_L2_PRESENT);
- ptdev->gpu_info.tiler_present = gpu_read64(ptdev, PWR_TILER_PRESENT);
- ptdev->gpu_info.shader_present = gpu_read64(ptdev, PWR_SHADER_PRESENT);
+ ptdev->gpu_info.l2_present = gpu_read64(ptdev->iomem, PWR_L2_PRESENT);
+ ptdev->gpu_info.tiler_present = gpu_read64(ptdev->iomem, PWR_TILER_PRESENT);
+ ptdev->gpu_info.shader_present = gpu_read64(ptdev->iomem, PWR_SHADER_PRESENT);
} else {
- ptdev->gpu_info.shader_present = gpu_read64(ptdev, GPU_SHADER_PRESENT);
- ptdev->gpu_info.tiler_present = gpu_read64(ptdev, GPU_TILER_PRESENT);
- ptdev->gpu_info.l2_present = gpu_read64(ptdev, GPU_L2_PRESENT);
+ ptdev->gpu_info.shader_present = gpu_read64(ptdev->iomem, GPU_SHADER_PRESENT);
+ ptdev->gpu_info.tiler_present = gpu_read64(ptdev->iomem, GPU_TILER_PRESENT);
+ ptdev->gpu_info.l2_present = gpu_read64(ptdev->iomem, GPU_L2_PRESENT);
}
return overload_shader_present(ptdev);
@@ -287,7 +290,7 @@ static int panthor_hw_bind_device(struct panthor_device *ptdev)
static int panthor_hw_gpu_id_init(struct panthor_device *ptdev)
{
- ptdev->gpu_info.gpu_id = gpu_read(ptdev, GPU_ID);
+ ptdev->gpu_info.gpu_id = gpu_read(ptdev->iomem, GPU_ID);
if (!ptdev->gpu_info.gpu_id)
return -ENXIO;
diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c b/drivers/gpu/drm/panthor/panthor_mmu.c
index fa8b31df85c9..0bd07a3dd774 100644
--- a/drivers/gpu/drm/panthor/panthor_mmu.c
+++ b/drivers/gpu/drm/panthor/panthor_mmu.c
@@ -522,9 +522,8 @@ static int wait_ready(struct panthor_device *ptdev, u32 as_nr)
/* Wait for the MMU status to indicate there is no active command, in
* case one is pending.
*/
- ret = gpu_read_relaxed_poll_timeout_atomic(ptdev, AS_STATUS(as_nr), val,
- !(val & AS_STATUS_AS_ACTIVE),
- 10, 100000);
+ ret = gpu_read_relaxed_poll_timeout_atomic(ptdev->iomem, AS_STATUS(as_nr), val,
+ !(val & AS_STATUS_AS_ACTIVE), 10, 100000);
if (ret) {
panthor_device_schedule_reset(ptdev);
@@ -541,7 +540,7 @@ static int as_send_cmd_and_wait(struct panthor_device *ptdev, u32 as_nr, u32 cmd
/* write AS_COMMAND when MMU is ready to accept another command */
status = wait_ready(ptdev, as_nr);
if (!status) {
- gpu_write(ptdev, AS_COMMAND(as_nr), cmd);
+ gpu_write(ptdev->iomem, AS_COMMAND(as_nr), cmd);
status = wait_ready(ptdev, as_nr);
}
@@ -592,9 +591,9 @@ static int panthor_mmu_as_enable(struct panthor_device *ptdev, u32 as_nr,
panthor_mmu_irq_enable_events(&ptdev->mmu->irq,
panthor_mmu_as_fault_mask(ptdev, as_nr));
- gpu_write64(ptdev, AS_TRANSTAB(as_nr), transtab);
- gpu_write64(ptdev, AS_MEMATTR(as_nr), memattr);
- gpu_write64(ptdev, AS_TRANSCFG(as_nr), transcfg);
+ gpu_write64(ptdev->iomem, AS_TRANSTAB(as_nr), transtab);
+ gpu_write64(ptdev->iomem, AS_MEMATTR(as_nr), memattr);
+ gpu_write64(ptdev->iomem, AS_TRANSCFG(as_nr), transcfg);
return as_send_cmd_and_wait(ptdev, as_nr, AS_COMMAND_UPDATE);
}
@@ -629,9 +628,9 @@ static int panthor_mmu_as_disable(struct panthor_device *ptdev, u32 as_nr,
if (recycle_slot)
return 0;
- gpu_write64(ptdev, AS_TRANSTAB(as_nr), 0);
- gpu_write64(ptdev, AS_MEMATTR(as_nr), 0);
- gpu_write64(ptdev, AS_TRANSCFG(as_nr), AS_TRANSCFG_ADRMODE_UNMAPPED);
+ gpu_write64(ptdev->iomem, AS_TRANSTAB(as_nr), 0);
+ gpu_write64(ptdev->iomem, AS_MEMATTR(as_nr), 0);
+ gpu_write64(ptdev->iomem, AS_TRANSCFG(as_nr), AS_TRANSCFG_ADRMODE_UNMAPPED);
return as_send_cmd_and_wait(ptdev, as_nr, AS_COMMAND_UPDATE);
}
@@ -784,7 +783,7 @@ int panthor_vm_active(struct panthor_vm *vm)
*/
fault_mask = panthor_mmu_as_fault_mask(ptdev, as);
if (ptdev->mmu->as.faulty_mask & fault_mask) {
- gpu_write(ptdev, MMU_INT_CLEAR, fault_mask);
+ gpu_write(ptdev->iomem, MMU_INT_CLEAR, fault_mask);
ptdev->mmu->as.faulty_mask &= ~fault_mask;
}
@@ -1712,7 +1711,7 @@ static int panthor_vm_lock_region(struct panthor_vm *vm, u64 start, u64 size)
mutex_lock(&ptdev->mmu->as.slots_lock);
if (vm->as.id >= 0 && size) {
/* Lock the region that needs to be updated */
- gpu_write64(ptdev, AS_LOCKADDR(vm->as.id),
+ gpu_write64(ptdev->iomem, AS_LOCKADDR(vm->as.id),
pack_region_range(ptdev, &start, &size));
/* If the lock succeeded, update the locked_region info. */
@@ -1773,8 +1772,8 @@ static void panthor_mmu_irq_handler(struct panthor_device *ptdev, u32 status)
u32 access_type;
u32 source_id;
- fault_status = gpu_read(ptdev, AS_FAULTSTATUS(as));
- addr = gpu_read64(ptdev, AS_FAULTADDRESS(as));
+ fault_status = gpu_read(ptdev->iomem, AS_FAULTSTATUS(as));
+ addr = gpu_read64(ptdev->iomem, AS_FAULTADDRESS(as));
/* decode the fault status */
exception_type = fault_status & 0xFF;
@@ -1805,7 +1804,7 @@ static void panthor_mmu_irq_handler(struct panthor_device *ptdev, u32 status)
* Note that COMPLETED irqs are never cleared, but this is fine
* because they are always masked.
*/
- gpu_write(ptdev, MMU_INT_CLEAR, mask);
+ gpu_write(ptdev->iomem, MMU_INT_CLEAR, mask);
if (ptdev->mmu->as.slots[as].vm)
ptdev->mmu->as.slots[as].vm->unhandled_fault = true;
diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/panthor/panthor_pwr.c
index ed3b2b4479ca..b77c85ad733a 100644
--- a/drivers/gpu/drm/panthor/panthor_pwr.c
+++ b/drivers/gpu/drm/panthor/panthor_pwr.c
@@ -55,7 +55,7 @@ struct panthor_pwr {
static void panthor_pwr_irq_handler(struct panthor_device *ptdev, u32 status)
{
spin_lock(&ptdev->pwr->reqs_lock);
- gpu_write(ptdev, PWR_INT_CLEAR, status);
+ gpu_write(ptdev->iomem, PWR_INT_CLEAR, status);
if (unlikely(status & PWR_IRQ_COMMAND_NOT_ALLOWED))
drm_err(&ptdev->base, "PWR_IRQ: COMMAND_NOT_ALLOWED");
@@ -74,14 +74,14 @@ PANTHOR_IRQ_HANDLER(pwr, PWR, panthor_pwr_irq_handler);
static void panthor_pwr_write_command(struct panthor_device *ptdev, u32 command, u64 args)
{
if (args)
- gpu_write64(ptdev, PWR_CMDARG, args);
+ gpu_write64(ptdev->iomem, PWR_CMDARG, args);
- gpu_write(ptdev, PWR_COMMAND, command);
+ gpu_write(ptdev->iomem, PWR_COMMAND, command);
}
static bool reset_irq_raised(struct panthor_device *ptdev)
{
- return gpu_read(ptdev, PWR_INT_RAWSTAT) & PWR_IRQ_RESET_COMPLETED;
+ return gpu_read(ptdev->iomem, PWR_INT_RAWSTAT) & PWR_IRQ_RESET_COMPLETED;
}
static bool reset_pending(struct panthor_device *ptdev)
@@ -96,7 +96,7 @@ static int panthor_pwr_reset(struct panthor_device *ptdev, u32 reset_cmd)
drm_WARN(&ptdev->base, 1, "Reset already pending");
} else {
ptdev->pwr->pending_reqs |= PWR_IRQ_RESET_COMPLETED;
- gpu_write(ptdev, PWR_INT_CLEAR, PWR_IRQ_RESET_COMPLETED);
+ gpu_write(ptdev->iomem, PWR_INT_CLEAR, PWR_IRQ_RESET_COMPLETED);
panthor_pwr_write_command(ptdev, reset_cmd, 0);
}
}
@@ -185,7 +185,7 @@ static int panthor_pwr_domain_wait_transition(struct panthor_device *ptdev, u32
u64 val;
int ret = 0;
- ret = gpu_read64_poll_timeout(ptdev, pwrtrans_reg, val, !(PWR_ALL_CORES_MASK & val), 100,
+ ret = gpu_read64_poll_timeout(ptdev->iomem, pwrtrans_reg, val, !(PWR_ALL_CORES_MASK & val), 100,
timeout_us);
if (ret) {
drm_err(&ptdev->base, "%s domain power in transition, pwrtrans(0x%llx)",
@@ -198,17 +198,17 @@ static int panthor_pwr_domain_wait_transition(struct panthor_device *ptdev, u32
static void panthor_pwr_debug_info_show(struct panthor_device *ptdev)
{
- drm_info(&ptdev->base, "GPU_FEATURES: 0x%016llx", gpu_read64(ptdev, GPU_FEATURES));
- drm_info(&ptdev->base, "PWR_STATUS: 0x%016llx", gpu_read64(ptdev, PWR_STATUS));
- drm_info(&ptdev->base, "L2_PRESENT: 0x%016llx", gpu_read64(ptdev, PWR_L2_PRESENT));
- drm_info(&ptdev->base, "L2_PWRTRANS: 0x%016llx", gpu_read64(ptdev, PWR_L2_PWRTRANS));
- drm_info(&ptdev->base, "L2_READY: 0x%016llx", gpu_read64(ptdev, PWR_L2_READY));
- drm_info(&ptdev->base, "TILER_PRESENT: 0x%016llx", gpu_read64(ptdev, PWR_TILER_PRESENT));
- drm_info(&ptdev->base, "TILER_PWRTRANS: 0x%016llx", gpu_read64(ptdev, PWR_TILER_PWRTRANS));
- drm_info(&ptdev->base, "TILER_READY: 0x%016llx", gpu_read64(ptdev, PWR_TILER_READY));
- drm_info(&ptdev->base, "SHADER_PRESENT: 0x%016llx", gpu_read64(ptdev, PWR_SHADER_PRESENT));
- drm_info(&ptdev->base, "SHADER_PWRTRANS: 0x%016llx", gpu_read64(ptdev, PWR_SHADER_PWRTRANS));
- drm_info(&ptdev->base, "SHADER_READY: 0x%016llx", gpu_read64(ptdev, PWR_SHADER_READY));
+ drm_info(&ptdev->base, "GPU_FEATURES: 0x%016llx", gpu_read64(ptdev->iomem, GPU_FEATURES));
+ drm_info(&ptdev->base, "PWR_STATUS: 0x%016llx", gpu_read64(ptdev->iomem, PWR_STATUS));
+ drm_info(&ptdev->base, "L2_PRESENT: 0x%016llx", gpu_read64(ptdev->iomem, PWR_L2_PRESENT));
+ drm_info(&ptdev->base, "L2_PWRTRANS: 0x%016llx", gpu_read64(ptdev->iomem, PWR_L2_PWRTRANS));
+ drm_info(&ptdev->base, "L2_READY: 0x%016llx", gpu_read64(ptdev->iomem, PWR_L2_READY));
+ drm_info(&ptdev->base, "TILER_PRESENT: 0x%016llx", gpu_read64(ptdev->iomem, PWR_TILER_PRESENT));
+ drm_info(&ptdev->base, "TILER_PWRTRANS: 0x%016llx", gpu_read64(ptdev->iomem, PWR_TILER_PWRTRANS));
+ drm_info(&ptdev->base, "TILER_READY: 0x%016llx", gpu_read64(ptdev->iomem, PWR_TILER_READY));
+ drm_info(&ptdev->base, "SHADER_PRESENT: 0x%016llx", gpu_read64(ptdev->iomem, PWR_SHADER_PRESENT));
+ drm_info(&ptdev->base, "SHADER_PWRTRANS: 0x%016llx", gpu_read64(ptdev->iomem, PWR_SHADER_PWRTRANS));
+ drm_info(&ptdev->base, "SHADER_READY: 0x%016llx", gpu_read64(ptdev->iomem, PWR_SHADER_READY));
}
static int panthor_pwr_domain_transition(struct panthor_device *ptdev, u32 cmd, u32 domain,
@@ -240,13 +240,13 @@ static int panthor_pwr_domain_transition(struct panthor_device *ptdev, u32 cmd,
return ret;
/* domain already in target state, return early */
- if ((gpu_read64(ptdev, ready_reg) & mask) == expected_val)
+ if ((gpu_read64(ptdev->iomem, ready_reg) & mask) == expected_val)
return 0;
panthor_pwr_write_command(ptdev, pwr_cmd, mask);
- ret = gpu_read64_poll_timeout(ptdev, ready_reg, val, (mask & val) == expected_val, 100,
- timeout_us);
+ ret = gpu_read64_poll_timeout(ptdev->iomem, ready_reg, val, (mask & val) == expected_val,
+ 100, timeout_us);
if (ret) {
drm_err(&ptdev->base,
"timeout waiting on %s power domain transition, cmd(0x%x), arg(0x%llx)",
@@ -279,7 +279,7 @@ static int panthor_pwr_domain_transition(struct panthor_device *ptdev, u32 cmd,
static int retract_domain(struct panthor_device *ptdev, u32 domain)
{
const u32 pwr_cmd = PWR_COMMAND_DEF(PWR_COMMAND_RETRACT, domain, 0);
- const u64 pwr_status = gpu_read64(ptdev, PWR_STATUS);
+ const u64 pwr_status = gpu_read64(ptdev->iomem, PWR_STATUS);
const u64 delegated_mask = PWR_STATUS_DOMAIN_DELEGATED(domain);
const u64 allow_mask = PWR_STATUS_DOMAIN_ALLOWED(domain);
u64 val;
@@ -288,8 +288,9 @@ static int retract_domain(struct panthor_device *ptdev, u32 domain)
if (drm_WARN_ON(&ptdev->base, domain == PWR_COMMAND_DOMAIN_L2))
return -EPERM;
- ret = gpu_read64_poll_timeout(ptdev, PWR_STATUS, val, !(PWR_STATUS_RETRACT_PENDING & val),
- 0, PWR_RETRACT_TIMEOUT_US);
+ ret = gpu_read64_poll_timeout(ptdev->iomem, PWR_STATUS, val,
+ !(PWR_STATUS_RETRACT_PENDING & val), 0,
+ PWR_RETRACT_TIMEOUT_US);
if (ret) {
drm_err(&ptdev->base, "%s domain retract pending", get_domain_name(domain));
return ret;
@@ -306,7 +307,7 @@ static int retract_domain(struct panthor_device *ptdev, u32 domain)
* On successful retraction
* allow-flag will be set with delegated-flag being cleared.
*/
- ret = gpu_read64_poll_timeout(ptdev, PWR_STATUS, val,
+ ret = gpu_read64_poll_timeout(ptdev->iomem, PWR_STATUS, val,
((delegated_mask | allow_mask) & val) == allow_mask, 10,
PWR_TRANSITION_TIMEOUT_US);
if (ret) {
@@ -333,7 +334,7 @@ static int retract_domain(struct panthor_device *ptdev, u32 domain)
static int delegate_domain(struct panthor_device *ptdev, u32 domain)
{
const u32 pwr_cmd = PWR_COMMAND_DEF(PWR_COMMAND_DELEGATE, domain, 0);
- const u64 pwr_status = gpu_read64(ptdev, PWR_STATUS);
+ const u64 pwr_status = gpu_read64(ptdev->iomem, PWR_STATUS);
const u64 allow_mask = PWR_STATUS_DOMAIN_ALLOWED(domain);
const u64 delegated_mask = PWR_STATUS_DOMAIN_DELEGATED(domain);
u64 val;
@@ -362,7 +363,7 @@ static int delegate_domain(struct panthor_device *ptdev, u32 domain)
* On successful delegation
* allow-flag will be cleared with delegated-flag being set.
*/
- ret = gpu_read64_poll_timeout(ptdev, PWR_STATUS, val,
+ ret = gpu_read64_poll_timeout(ptdev->iomem, PWR_STATUS, val,
((delegated_mask | allow_mask) & val) == delegated_mask,
10, PWR_TRANSITION_TIMEOUT_US);
if (ret) {
@@ -410,7 +411,7 @@ static int panthor_pwr_delegate_domains(struct panthor_device *ptdev)
*/
static int panthor_pwr_domain_force_off(struct panthor_device *ptdev, u32 domain)
{
- const u64 domain_ready = gpu_read64(ptdev, get_domain_ready_reg(domain));
+ const u64 domain_ready = gpu_read64(ptdev->iomem, get_domain_ready_reg(domain));
int ret;
/* Domain already powered down, early exit. */
@@ -471,7 +472,7 @@ int panthor_pwr_init(struct panthor_device *ptdev)
int panthor_pwr_reset_soft(struct panthor_device *ptdev)
{
- if (!(gpu_read64(ptdev, PWR_STATUS) & PWR_STATUS_ALLOW_SOFT_RESET)) {
+ if (!(gpu_read64(ptdev->iomem, PWR_STATUS) & PWR_STATUS_ALLOW_SOFT_RESET)) {
drm_err(&ptdev->base, "RESET_SOFT not allowed");
return -EOPNOTSUPP;
}
@@ -482,7 +483,7 @@ int panthor_pwr_reset_soft(struct panthor_device *ptdev)
void panthor_pwr_l2_power_off(struct panthor_device *ptdev)
{
const u64 l2_allow_mask = PWR_STATUS_DOMAIN_ALLOWED(PWR_COMMAND_DOMAIN_L2);
- const u64 pwr_status = gpu_read64(ptdev, PWR_STATUS);
+ const u64 pwr_status = gpu_read64(ptdev->iomem, PWR_STATUS);
/* Abort if L2 power off constraints are not satisfied */
if (!(pwr_status & l2_allow_mask)) {
@@ -508,7 +509,7 @@ void panthor_pwr_l2_power_off(struct panthor_device *ptdev)
int panthor_pwr_l2_power_on(struct panthor_device *ptdev)
{
- const u32 pwr_status = gpu_read64(ptdev, PWR_STATUS);
+ const u32 pwr_status = gpu_read64(ptdev->iomem, PWR_STATUS);
const u32 l2_allow_mask = PWR_STATUS_DOMAIN_ALLOWED(PWR_COMMAND_DOMAIN_L2);
int ret;
diff --git a/drivers/gpu/drm/panthor/panthor_sched.c b/drivers/gpu/drm/panthor/panthor_sched.c
index a06d91875beb..7c8d350da02f 100644
--- a/drivers/gpu/drm/panthor/panthor_sched.c
+++ b/drivers/gpu/drm/panthor/panthor_sched.c
@@ -3372,7 +3372,7 @@ queue_run_job(struct drm_sched_job *sched_job)
if (resume_tick)
sched_resume_tick(ptdev);
- gpu_write(ptdev, CSF_DOORBELL(queue->doorbell_id), 1);
+ gpu_write(ptdev->iomem, CSF_DOORBELL(queue->doorbell_id), 1);
if (!sched->pm.has_ref &&
!(group->blocked_queues & BIT(job->queue_idx))) {
pm_runtime_get(ptdev->base.dev);
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 1/8] drm/panthor: Pass an iomem pointer to GPU register access helpers
2026-04-10 16:46 ` [PATCH 1/8] drm/panthor: Pass an iomem pointer to GPU register access helpers Karunika Choo
@ 2026-04-10 18:11 ` Boris Brezillon
0 siblings, 0 replies; 17+ messages in thread
From: Boris Brezillon @ 2026-04-10 18:11 UTC (permalink / raw)
To: Karunika Choo
Cc: dri-devel, nd, Steven Price, Liviu Dudau, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
linux-kernel
On Fri, 10 Apr 2026 17:46:30 +0100
Karunika Choo <karunika.choo@arm.com> wrote:
> Convert the Panthor register access helpers to take an iomem pointer
> instead of a panthor_device pointer.
>
> This makes the helpers usable with block-local registers instead of
> routing all accesses to go through ptdev->iomem. It is a preparatory
> change for splitting the register space by components and for moving
> callers away from cross-component register accesses.
>
> No functional change intended.
>
> Signed-off-by: Karunika Choo <karunika.choo@arm.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
> ---
> drivers/gpu/drm/panthor/panthor_device.c | 2 +-
> drivers/gpu/drm/panthor/panthor_device.h | 78 ++++++++++++------------
> drivers/gpu/drm/panthor/panthor_drv.c | 6 +-
> drivers/gpu/drm/panthor/panthor_fw.c | 22 +++----
> drivers/gpu/drm/panthor/panthor_gpu.c | 42 ++++++-------
> drivers/gpu/drm/panthor/panthor_hw.c | 47 +++++++-------
> drivers/gpu/drm/panthor/panthor_mmu.c | 29 +++++----
> drivers/gpu/drm/panthor/panthor_pwr.c | 61 +++++++++---------
> drivers/gpu/drm/panthor/panthor_sched.c | 2 +-
> 9 files changed, 146 insertions(+), 143 deletions(-)
>
> diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/panthor/panthor_device.c
> index bc62a498a8a8..d62017b73409 100644
> --- a/drivers/gpu/drm/panthor/panthor_device.c
> +++ b/drivers/gpu/drm/panthor/panthor_device.c
> @@ -43,7 +43,7 @@ static int panthor_gpu_coherency_init(struct panthor_device *ptdev)
> /* Check if the ACE-Lite coherency protocol is actually supported by the GPU.
> * ACE protocol has never been supported for command stream frontend GPUs.
> */
> - if ((gpu_read(ptdev, GPU_COHERENCY_FEATURES) &
> + if ((gpu_read(ptdev->iomem, GPU_COHERENCY_FEATURES) &
> GPU_COHERENCY_PROT_BIT(ACE_LITE))) {
> ptdev->gpu_info.selected_coherency = GPU_COHERENCY_ACE_LITE;
> return 0;
> diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/panthor/panthor_device.h
> index 5cba272f9b4d..285bf7e4439e 100644
> --- a/drivers/gpu/drm/panthor/panthor_device.h
> +++ b/drivers/gpu/drm/panthor/panthor_device.h
> @@ -505,7 +505,7 @@ static irqreturn_t panthor_ ## __name ## _irq_raw_handler(int irq, void *data)
> struct panthor_device *ptdev = pirq->ptdev; \
> enum panthor_irq_state old_state; \
> \
> - if (!gpu_read(ptdev, __reg_prefix ## _INT_STAT)) \
> + if (!gpu_read(ptdev->iomem, __reg_prefix ## _INT_STAT)) \
> return IRQ_NONE; \
> \
> guard(spinlock_irqsave)(&pirq->mask_lock); \
> @@ -515,7 +515,7 @@ static irqreturn_t panthor_ ## __name ## _irq_raw_handler(int irq, void *data)
> if (old_state != PANTHOR_IRQ_STATE_ACTIVE) \
> return IRQ_NONE; \
> \
> - gpu_write(ptdev, __reg_prefix ## _INT_MASK, 0); \
> + gpu_write(ptdev->iomem, __reg_prefix ## _INT_MASK, 0); \
> return IRQ_WAKE_THREAD; \
> } \
> \
> @@ -534,7 +534,7 @@ static irqreturn_t panthor_ ## __name ## _irq_threaded_handler(int irq, void *da
> * right before the HW event kicks in. TLDR; it's all expected races we're \
> * covered for. \
> */ \
> - u32 status = gpu_read(ptdev, __reg_prefix ## _INT_RAWSTAT) & pirq->mask; \
> + u32 status = gpu_read(ptdev->iomem, __reg_prefix ## _INT_RAWSTAT) & pirq->mask; \
> \
> if (!status) \
> break; \
> @@ -550,7 +550,7 @@ static irqreturn_t panthor_ ## __name ## _irq_threaded_handler(int irq, void *da
> PANTHOR_IRQ_STATE_PROCESSING, \
> PANTHOR_IRQ_STATE_ACTIVE); \
> if (old_state == PANTHOR_IRQ_STATE_PROCESSING) \
> - gpu_write(ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \
> + gpu_write(ptdev->iomem, __reg_prefix ## _INT_MASK, pirq->mask); \
> } \
> \
> return ret; \
> @@ -560,7 +560,7 @@ static inline void panthor_ ## __name ## _irq_suspend(struct panthor_irq *pirq)
> { \
> scoped_guard(spinlock_irqsave, &pirq->mask_lock) { \
> atomic_set(&pirq->state, PANTHOR_IRQ_STATE_SUSPENDING); \
> - gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, 0); \
> + gpu_write(pirq->ptdev->iomem, __reg_prefix ## _INT_MASK, 0); \
> } \
> synchronize_irq(pirq->irq); \
> atomic_set(&pirq->state, PANTHOR_IRQ_STATE_SUSPENDED); \
> @@ -571,8 +571,8 @@ static inline void panthor_ ## __name ## _irq_resume(struct panthor_irq *pirq)
> guard(spinlock_irqsave)(&pirq->mask_lock); \
> \
> atomic_set(&pirq->state, PANTHOR_IRQ_STATE_ACTIVE); \
> - gpu_write(pirq->ptdev, __reg_prefix ## _INT_CLEAR, pirq->mask); \
> - gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \
> + gpu_write(pirq->ptdev->iomem, __reg_prefix ## _INT_CLEAR, pirq->mask); \
> + gpu_write(pirq->ptdev->iomem, __reg_prefix ## _INT_MASK, pirq->mask); \
> } \
> \
> static int panthor_request_ ## __name ## _irq(struct panthor_device *ptdev, \
> @@ -603,7 +603,7 @@ static inline void panthor_ ## __name ## _irq_enable_events(struct panthor_irq *
> * If the IRQ is suspended/suspending, the mask is restored at resume time. \
> */ \
> if (atomic_read(&pirq->state) == PANTHOR_IRQ_STATE_ACTIVE) \
> - gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \
> + gpu_write(pirq->ptdev->iomem, __reg_prefix ## _INT_MASK, pirq->mask); \
> } \
> \
> static inline void panthor_ ## __name ## _irq_disable_events(struct panthor_irq *pirq, u32 mask)\
> @@ -617,80 +617,80 @@ static inline void panthor_ ## __name ## _irq_disable_events(struct panthor_irq
> * If the IRQ is suspended/suspending, the mask is restored at resume time. \
> */ \
> if (atomic_read(&pirq->state) == PANTHOR_IRQ_STATE_ACTIVE) \
> - gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \
> + gpu_write(pirq->ptdev->iomem, __reg_prefix ## _INT_MASK, pirq->mask); \
> }
>
> extern struct workqueue_struct *panthor_cleanup_wq;
>
> -static inline void gpu_write(struct panthor_device *ptdev, u32 reg, u32 data)
> +static inline void gpu_write(void __iomem *iomem, u32 reg, u32 data)
> {
> - writel(data, ptdev->iomem + reg);
> + writel(data, iomem + reg);
> }
>
> -static inline u32 gpu_read(struct panthor_device *ptdev, u32 reg)
> +static inline u32 gpu_read(void __iomem *iomem, u32 reg)
> {
> - return readl(ptdev->iomem + reg);
> + return readl(iomem + reg);
> }
>
> -static inline u32 gpu_read_relaxed(struct panthor_device *ptdev, u32 reg)
> +static inline u32 gpu_read_relaxed(void __iomem *iomem, u32 reg)
> {
> - return readl_relaxed(ptdev->iomem + reg);
> + return readl_relaxed(iomem + reg);
> }
>
> -static inline void gpu_write64(struct panthor_device *ptdev, u32 reg, u64 data)
> +static inline void gpu_write64(void __iomem *iomem, u32 reg, u64 data)
> {
> - gpu_write(ptdev, reg, lower_32_bits(data));
> - gpu_write(ptdev, reg + 4, upper_32_bits(data));
> + gpu_write(iomem, reg, lower_32_bits(data));
> + gpu_write(iomem, reg + 4, upper_32_bits(data));
> }
>
> -static inline u64 gpu_read64(struct panthor_device *ptdev, u32 reg)
> +static inline u64 gpu_read64(void __iomem *iomem, u32 reg)
> {
> - return (gpu_read(ptdev, reg) | ((u64)gpu_read(ptdev, reg + 4) << 32));
> + return (gpu_read(iomem, reg) | ((u64)gpu_read(iomem, reg + 4) << 32));
> }
>
> -static inline u64 gpu_read64_relaxed(struct panthor_device *ptdev, u32 reg)
> +static inline u64 gpu_read64_relaxed(void __iomem *iomem, u32 reg)
> {
> - return (gpu_read_relaxed(ptdev, reg) |
> - ((u64)gpu_read_relaxed(ptdev, reg + 4) << 32));
> + return (gpu_read_relaxed(iomem, reg) |
> + ((u64)gpu_read_relaxed(iomem, reg + 4) << 32));
> }
>
> -static inline u64 gpu_read64_counter(struct panthor_device *ptdev, u32 reg)
> +static inline u64 gpu_read64_counter(void __iomem *iomem, u32 reg)
> {
> u32 lo, hi1, hi2;
> do {
> - hi1 = gpu_read(ptdev, reg + 4);
> - lo = gpu_read(ptdev, reg);
> - hi2 = gpu_read(ptdev, reg + 4);
> + hi1 = gpu_read(iomem, reg + 4);
> + lo = gpu_read(iomem, reg);
> + hi2 = gpu_read(iomem, reg + 4);
> } while (hi1 != hi2);
> return lo | ((u64)hi2 << 32);
> }
>
> -#define gpu_read_poll_timeout(dev, reg, val, cond, delay_us, timeout_us) \
> +#define gpu_read_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us) \
> read_poll_timeout(gpu_read, val, cond, delay_us, timeout_us, false, \
> - dev, reg)
> + iomem, reg)
>
> -#define gpu_read_poll_timeout_atomic(dev, reg, val, cond, delay_us, \
> +#define gpu_read_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \
> timeout_us) \
> read_poll_timeout_atomic(gpu_read, val, cond, delay_us, timeout_us, \
> - false, dev, reg)
> + false, iomem, reg)
>
> -#define gpu_read64_poll_timeout(dev, reg, val, cond, delay_us, timeout_us) \
> +#define gpu_read64_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us) \
> read_poll_timeout(gpu_read64, val, cond, delay_us, timeout_us, false, \
> - dev, reg)
> + iomem, reg)
>
> -#define gpu_read64_poll_timeout_atomic(dev, reg, val, cond, delay_us, \
> +#define gpu_read64_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \
> timeout_us) \
> read_poll_timeout_atomic(gpu_read64, val, cond, delay_us, timeout_us, \
> - false, dev, reg)
> + false, iomem, reg)
>
> -#define gpu_read_relaxed_poll_timeout_atomic(dev, reg, val, cond, delay_us, \
> +#define gpu_read_relaxed_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \
> timeout_us) \
> read_poll_timeout_atomic(gpu_read_relaxed, val, cond, delay_us, \
> - timeout_us, false, dev, reg)
> + timeout_us, false, iomem, reg)
>
> -#define gpu_read64_relaxed_poll_timeout(dev, reg, val, cond, delay_us, \
> +#define gpu_read64_relaxed_poll_timeout(iomem, reg, val, cond, delay_us, \
> timeout_us) \
> read_poll_timeout(gpu_read64_relaxed, val, cond, delay_us, timeout_us, \
> - false, dev, reg)
> + false, iomem, reg)
>
> #endif
> diff --git a/drivers/gpu/drm/panthor/panthor_drv.c b/drivers/gpu/drm/panthor/panthor_drv.c
> index 73fc983dc9b4..4f926c861fba 100644
> --- a/drivers/gpu/drm/panthor/panthor_drv.c
> +++ b/drivers/gpu/drm/panthor/panthor_drv.c
> @@ -839,7 +839,7 @@ static int panthor_query_timestamp_info(struct panthor_device *ptdev,
> }
>
> if (flags & DRM_PANTHOR_TIMESTAMP_GPU_OFFSET)
> - arg->timestamp_offset = gpu_read64(ptdev, GPU_TIMESTAMP_OFFSET);
> + arg->timestamp_offset = gpu_read64(ptdev->iomem, GPU_TIMESTAMP_OFFSET);
> else
> arg->timestamp_offset = 0;
>
> @@ -854,7 +854,7 @@ static int panthor_query_timestamp_info(struct panthor_device *ptdev,
> query_start_time = 0;
>
> if (flags & DRM_PANTHOR_TIMESTAMP_GPU)
> - arg->current_timestamp = gpu_read64_counter(ptdev, GPU_TIMESTAMP);
> + arg->current_timestamp = gpu_read64_counter(ptdev->iomem, GPU_TIMESTAMP);
> else
> arg->current_timestamp = 0;
>
> @@ -870,7 +870,7 @@ static int panthor_query_timestamp_info(struct panthor_device *ptdev,
> }
>
> if (flags & DRM_PANTHOR_TIMESTAMP_GPU_CYCLE_COUNT)
> - arg->cycle_count = gpu_read64_counter(ptdev, GPU_CYCLE_COUNT);
> + arg->cycle_count = gpu_read64_counter(ptdev->iomem, GPU_CYCLE_COUNT);
> else
> arg->cycle_count = 0;
>
> diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor/panthor_fw.c
> index be0da5b1f3ab..69a19751a314 100644
> --- a/drivers/gpu/drm/panthor/panthor_fw.c
> +++ b/drivers/gpu/drm/panthor/panthor_fw.c
> @@ -1054,7 +1054,7 @@ static void panthor_fw_init_global_iface(struct panthor_device *ptdev)
> GLB_CFG_POWEROFF_TIMER |
> GLB_CFG_PROGRESS_TIMER);
>
> - gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
> + gpu_write(ptdev->iomem, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
>
> /* Kick the watchdog. */
> mod_delayed_work(ptdev->reset.wq, &ptdev->fw->watchdog.ping_work,
> @@ -1069,7 +1069,7 @@ static void panthor_job_irq_handler(struct panthor_device *ptdev, u32 status)
> if (tracepoint_enabled(gpu_job_irq))
> start = ktime_get_ns();
>
> - gpu_write(ptdev, JOB_INT_CLEAR, status);
> + gpu_write(ptdev->iomem, JOB_INT_CLEAR, status);
>
> if (!ptdev->fw->booted && (status & JOB_INT_GLOBAL_IF))
> ptdev->fw->booted = true;
> @@ -1097,13 +1097,13 @@ static int panthor_fw_start(struct panthor_device *ptdev)
> ptdev->fw->booted = false;
> panthor_job_irq_enable_events(&ptdev->fw->irq, ~0);
> panthor_job_irq_resume(&ptdev->fw->irq);
> - gpu_write(ptdev, MCU_CONTROL, MCU_CONTROL_AUTO);
> + gpu_write(ptdev->iomem, MCU_CONTROL, MCU_CONTROL_AUTO);
>
> if (!wait_event_timeout(ptdev->fw->req_waitqueue,
> ptdev->fw->booted,
> msecs_to_jiffies(1000))) {
> if (!ptdev->fw->booted &&
> - !(gpu_read(ptdev, JOB_INT_STAT) & JOB_INT_GLOBAL_IF))
> + !(gpu_read(ptdev->iomem, JOB_INT_STAT) & JOB_INT_GLOBAL_IF))
> timedout = true;
> }
>
> @@ -1114,7 +1114,7 @@ static int panthor_fw_start(struct panthor_device *ptdev)
> [MCU_STATUS_HALT] = "halt",
> [MCU_STATUS_FATAL] = "fatal",
> };
> - u32 status = gpu_read(ptdev, MCU_STATUS);
> + u32 status = gpu_read(ptdev->iomem, MCU_STATUS);
>
> drm_err(&ptdev->base, "Failed to boot MCU (status=%s)",
> status < ARRAY_SIZE(status_str) ? status_str[status] : "unknown");
> @@ -1128,8 +1128,8 @@ static void panthor_fw_stop(struct panthor_device *ptdev)
> {
> u32 status;
>
> - gpu_write(ptdev, MCU_CONTROL, MCU_CONTROL_DISABLE);
> - if (gpu_read_poll_timeout(ptdev, MCU_STATUS, status,
> + gpu_write(ptdev->iomem, MCU_CONTROL, MCU_CONTROL_DISABLE);
> + if (gpu_read_poll_timeout(ptdev->iomem, MCU_STATUS, status,
> status == MCU_STATUS_DISABLED, 10, 100000))
> drm_err(&ptdev->base, "Failed to stop MCU");
> }
> @@ -1139,7 +1139,7 @@ static bool panthor_fw_mcu_halted(struct panthor_device *ptdev)
> struct panthor_fw_global_iface *glb_iface = panthor_fw_get_glb_iface(ptdev);
> bool halted;
>
> - halted = gpu_read(ptdev, MCU_STATUS) == MCU_STATUS_HALT;
> + halted = gpu_read(ptdev->iomem, MCU_STATUS) == MCU_STATUS_HALT;
>
> if (panthor_fw_has_glb_state(ptdev))
> halted &= (GLB_STATE_GET(glb_iface->output->ack) == GLB_STATE_HALT);
> @@ -1156,7 +1156,7 @@ static void panthor_fw_halt_mcu(struct panthor_device *ptdev)
> else
> panthor_fw_update_reqs(glb_iface, req, GLB_HALT, GLB_HALT);
>
> - gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
> + gpu_write(ptdev->iomem, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
> }
>
> static bool panthor_fw_wait_mcu_halted(struct panthor_device *ptdev)
> @@ -1414,7 +1414,7 @@ void panthor_fw_ring_csg_doorbells(struct panthor_device *ptdev, u32 csg_mask)
> struct panthor_fw_global_iface *glb_iface = panthor_fw_get_glb_iface(ptdev);
>
> panthor_fw_toggle_reqs(glb_iface, doorbell_req, doorbell_ack, csg_mask);
> - gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
> + gpu_write(ptdev->iomem, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
> }
>
> static void panthor_fw_ping_work(struct work_struct *work)
> @@ -1429,7 +1429,7 @@ static void panthor_fw_ping_work(struct work_struct *work)
> return;
>
> panthor_fw_toggle_reqs(glb_iface, req, ack, GLB_PING);
> - gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
> + gpu_write(ptdev->iomem, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
>
> ret = panthor_fw_glb_wait_acks(ptdev, GLB_PING, &acked, 100);
> if (ret) {
> diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c
> index 2ab444ee8c71..bdb72cebccb3 100644
> --- a/drivers/gpu/drm/panthor/panthor_gpu.c
> +++ b/drivers/gpu/drm/panthor/panthor_gpu.c
> @@ -56,7 +56,7 @@ struct panthor_gpu {
>
> static void panthor_gpu_coherency_set(struct panthor_device *ptdev)
> {
> - gpu_write(ptdev, GPU_COHERENCY_PROTOCOL,
> + gpu_write(ptdev->iomem, GPU_COHERENCY_PROTOCOL,
> ptdev->gpu_info.selected_coherency);
> }
>
> @@ -75,26 +75,26 @@ static void panthor_gpu_l2_config_set(struct panthor_device *ptdev)
> }
>
> for (i = 0; i < ARRAY_SIZE(data->asn_hash); i++)
> - gpu_write(ptdev, GPU_ASN_HASH(i), data->asn_hash[i]);
> + gpu_write(ptdev->iomem, GPU_ASN_HASH(i), data->asn_hash[i]);
>
> - l2_config = gpu_read(ptdev, GPU_L2_CONFIG);
> + l2_config = gpu_read(ptdev->iomem, GPU_L2_CONFIG);
> l2_config |= GPU_L2_CONFIG_ASN_HASH_ENABLE;
> - gpu_write(ptdev, GPU_L2_CONFIG, l2_config);
> + gpu_write(ptdev->iomem, GPU_L2_CONFIG, l2_config);
> }
>
> static void panthor_gpu_irq_handler(struct panthor_device *ptdev, u32 status)
> {
> - gpu_write(ptdev, GPU_INT_CLEAR, status);
> + gpu_write(ptdev->iomem, GPU_INT_CLEAR, status);
>
> if (tracepoint_enabled(gpu_power_status) && (status & GPU_POWER_INTERRUPTS_MASK))
> trace_gpu_power_status(ptdev->base.dev,
> - gpu_read64(ptdev, SHADER_READY),
> - gpu_read64(ptdev, TILER_READY),
> - gpu_read64(ptdev, L2_READY));
> + gpu_read64(ptdev->iomem, SHADER_READY),
> + gpu_read64(ptdev->iomem, TILER_READY),
> + gpu_read64(ptdev->iomem, L2_READY));
>
> if (status & GPU_IRQ_FAULT) {
> - u32 fault_status = gpu_read(ptdev, GPU_FAULT_STATUS);
> - u64 address = gpu_read64(ptdev, GPU_FAULT_ADDR);
> + u32 fault_status = gpu_read(ptdev->iomem, GPU_FAULT_STATUS);
> + u64 address = gpu_read64(ptdev->iomem, GPU_FAULT_ADDR);
>
> drm_warn(&ptdev->base, "GPU Fault 0x%08x (%s) at 0x%016llx\n",
> fault_status, panthor_exception_name(ptdev, fault_status & 0xFF),
> @@ -204,7 +204,7 @@ int panthor_gpu_block_power_off(struct panthor_device *ptdev,
> u32 val;
> int ret;
>
> - ret = gpu_read64_relaxed_poll_timeout(ptdev, pwrtrans_reg, val,
> + ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, pwrtrans_reg, val,
> !(mask & val), 100, timeout_us);
> if (ret) {
> drm_err(&ptdev->base,
> @@ -213,9 +213,9 @@ int panthor_gpu_block_power_off(struct panthor_device *ptdev,
> return ret;
> }
>
> - gpu_write64(ptdev, pwroff_reg, mask);
> + gpu_write64(ptdev->iomem, pwroff_reg, mask);
>
> - ret = gpu_read64_relaxed_poll_timeout(ptdev, pwrtrans_reg, val,
> + ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, pwrtrans_reg, val,
> !(mask & val), 100, timeout_us);
> if (ret) {
> drm_err(&ptdev->base,
> @@ -247,7 +247,7 @@ int panthor_gpu_block_power_on(struct panthor_device *ptdev,
> u32 val;
> int ret;
>
> - ret = gpu_read64_relaxed_poll_timeout(ptdev, pwrtrans_reg, val,
> + ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, pwrtrans_reg, val,
> !(mask & val), 100, timeout_us);
> if (ret) {
> drm_err(&ptdev->base,
> @@ -256,9 +256,9 @@ int panthor_gpu_block_power_on(struct panthor_device *ptdev,
> return ret;
> }
>
> - gpu_write64(ptdev, pwron_reg, mask);
> + gpu_write64(ptdev->iomem, pwron_reg, mask);
>
> - ret = gpu_read64_relaxed_poll_timeout(ptdev, rdy_reg, val,
> + ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, rdy_reg, val,
> (mask & val) == val,
> 100, timeout_us);
> if (ret) {
> @@ -326,7 +326,7 @@ int panthor_gpu_flush_caches(struct panthor_device *ptdev,
> spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
> if (!(ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED)) {
> ptdev->gpu->pending_reqs |= GPU_IRQ_CLEAN_CACHES_COMPLETED;
> - gpu_write(ptdev, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other));
> + gpu_write(ptdev->iomem, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other));
> } else {
> ret = -EIO;
> }
> @@ -340,7 +340,7 @@ int panthor_gpu_flush_caches(struct panthor_device *ptdev,
> msecs_to_jiffies(100))) {
> spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
> if ((ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED) != 0 &&
> - !(gpu_read(ptdev, GPU_INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED))
> + !(gpu_read(ptdev->iomem, GPU_INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED))
> ret = -ETIMEDOUT;
> else
> ptdev->gpu->pending_reqs &= ~GPU_IRQ_CLEAN_CACHES_COMPLETED;
> @@ -370,8 +370,8 @@ int panthor_gpu_soft_reset(struct panthor_device *ptdev)
> if (!drm_WARN_ON(&ptdev->base,
> ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED)) {
> ptdev->gpu->pending_reqs |= GPU_IRQ_RESET_COMPLETED;
> - gpu_write(ptdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED);
> - gpu_write(ptdev, GPU_CMD, GPU_SOFT_RESET);
> + gpu_write(ptdev->iomem, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED);
> + gpu_write(ptdev->iomem, GPU_CMD, GPU_SOFT_RESET);
> }
> spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags);
>
> @@ -380,7 +380,7 @@ int panthor_gpu_soft_reset(struct panthor_device *ptdev)
> msecs_to_jiffies(100))) {
> spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
> if ((ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED) != 0 &&
> - !(gpu_read(ptdev, GPU_INT_RAWSTAT) & GPU_IRQ_RESET_COMPLETED))
> + !(gpu_read(ptdev->iomem, GPU_INT_RAWSTAT) & GPU_IRQ_RESET_COMPLETED))
> timedout = true;
> else
> ptdev->gpu->pending_reqs &= ~GPU_IRQ_RESET_COMPLETED;
> diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor/panthor_hw.c
> index d135aa6724fa..9309d0938212 100644
> --- a/drivers/gpu/drm/panthor/panthor_hw.c
> +++ b/drivers/gpu/drm/panthor/panthor_hw.c
> @@ -194,35 +194,38 @@ static int panthor_gpu_info_init(struct panthor_device *ptdev)
> {
> unsigned int i;
>
> - ptdev->gpu_info.csf_id = gpu_read(ptdev, GPU_CSF_ID);
> - ptdev->gpu_info.gpu_rev = gpu_read(ptdev, GPU_REVID);
> - ptdev->gpu_info.core_features = gpu_read(ptdev, GPU_CORE_FEATURES);
> - ptdev->gpu_info.l2_features = gpu_read(ptdev, GPU_L2_FEATURES);
> - ptdev->gpu_info.tiler_features = gpu_read(ptdev, GPU_TILER_FEATURES);
> - ptdev->gpu_info.mem_features = gpu_read(ptdev, GPU_MEM_FEATURES);
> - ptdev->gpu_info.mmu_features = gpu_read(ptdev, GPU_MMU_FEATURES);
> - ptdev->gpu_info.thread_features = gpu_read(ptdev, GPU_THREAD_FEATURES);
> - ptdev->gpu_info.max_threads = gpu_read(ptdev, GPU_THREAD_MAX_THREADS);
> - ptdev->gpu_info.thread_max_workgroup_size = gpu_read(ptdev, GPU_THREAD_MAX_WORKGROUP_SIZE);
> - ptdev->gpu_info.thread_max_barrier_size = gpu_read(ptdev, GPU_THREAD_MAX_BARRIER_SIZE);
> - ptdev->gpu_info.coherency_features = gpu_read(ptdev, GPU_COHERENCY_FEATURES);
> + ptdev->gpu_info.csf_id = gpu_read(ptdev->iomem, GPU_CSF_ID);
> + ptdev->gpu_info.gpu_rev = gpu_read(ptdev->iomem, GPU_REVID);
> + ptdev->gpu_info.core_features = gpu_read(ptdev->iomem, GPU_CORE_FEATURES);
> + ptdev->gpu_info.l2_features = gpu_read(ptdev->iomem, GPU_L2_FEATURES);
> + ptdev->gpu_info.tiler_features = gpu_read(ptdev->iomem, GPU_TILER_FEATURES);
> + ptdev->gpu_info.mem_features = gpu_read(ptdev->iomem, GPU_MEM_FEATURES);
> + ptdev->gpu_info.mmu_features = gpu_read(ptdev->iomem, GPU_MMU_FEATURES);
> + ptdev->gpu_info.thread_features = gpu_read(ptdev->iomem, GPU_THREAD_FEATURES);
> + ptdev->gpu_info.max_threads = gpu_read(ptdev->iomem, GPU_THREAD_MAX_THREADS);
> + ptdev->gpu_info.thread_max_workgroup_size =
> + gpu_read(ptdev->iomem, GPU_THREAD_MAX_WORKGROUP_SIZE);
> + ptdev->gpu_info.thread_max_barrier_size =
> + gpu_read(ptdev->iomem, GPU_THREAD_MAX_BARRIER_SIZE);
> + ptdev->gpu_info.coherency_features = gpu_read(ptdev->iomem, GPU_COHERENCY_FEATURES);
> for (i = 0; i < 4; i++)
> - ptdev->gpu_info.texture_features[i] = gpu_read(ptdev, GPU_TEXTURE_FEATURES(i));
> + ptdev->gpu_info.texture_features[i] =
> + gpu_read(ptdev->iomem, GPU_TEXTURE_FEATURES(i));
>
> - ptdev->gpu_info.as_present = gpu_read(ptdev, GPU_AS_PRESENT);
> + ptdev->gpu_info.as_present = gpu_read(ptdev->iomem, GPU_AS_PRESENT);
>
> /* Introduced in arch 11.x */
> - ptdev->gpu_info.gpu_features = gpu_read64(ptdev, GPU_FEATURES);
> + ptdev->gpu_info.gpu_features = gpu_read64(ptdev->iomem, GPU_FEATURES);
>
> if (panthor_hw_has_pwr_ctrl(ptdev)) {
> /* Introduced in arch 14.x */
> - ptdev->gpu_info.l2_present = gpu_read64(ptdev, PWR_L2_PRESENT);
> - ptdev->gpu_info.tiler_present = gpu_read64(ptdev, PWR_TILER_PRESENT);
> - ptdev->gpu_info.shader_present = gpu_read64(ptdev, PWR_SHADER_PRESENT);
> + ptdev->gpu_info.l2_present = gpu_read64(ptdev->iomem, PWR_L2_PRESENT);
> + ptdev->gpu_info.tiler_present = gpu_read64(ptdev->iomem, PWR_TILER_PRESENT);
> + ptdev->gpu_info.shader_present = gpu_read64(ptdev->iomem, PWR_SHADER_PRESENT);
> } else {
> - ptdev->gpu_info.shader_present = gpu_read64(ptdev, GPU_SHADER_PRESENT);
> - ptdev->gpu_info.tiler_present = gpu_read64(ptdev, GPU_TILER_PRESENT);
> - ptdev->gpu_info.l2_present = gpu_read64(ptdev, GPU_L2_PRESENT);
> + ptdev->gpu_info.shader_present = gpu_read64(ptdev->iomem, GPU_SHADER_PRESENT);
> + ptdev->gpu_info.tiler_present = gpu_read64(ptdev->iomem, GPU_TILER_PRESENT);
> + ptdev->gpu_info.l2_present = gpu_read64(ptdev->iomem, GPU_L2_PRESENT);
> }
>
> return overload_shader_present(ptdev);
> @@ -287,7 +290,7 @@ static int panthor_hw_bind_device(struct panthor_device *ptdev)
>
> static int panthor_hw_gpu_id_init(struct panthor_device *ptdev)
> {
> - ptdev->gpu_info.gpu_id = gpu_read(ptdev, GPU_ID);
> + ptdev->gpu_info.gpu_id = gpu_read(ptdev->iomem, GPU_ID);
> if (!ptdev->gpu_info.gpu_id)
> return -ENXIO;
>
> diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c b/drivers/gpu/drm/panthor/panthor_mmu.c
> index fa8b31df85c9..0bd07a3dd774 100644
> --- a/drivers/gpu/drm/panthor/panthor_mmu.c
> +++ b/drivers/gpu/drm/panthor/panthor_mmu.c
> @@ -522,9 +522,8 @@ static int wait_ready(struct panthor_device *ptdev, u32 as_nr)
> /* Wait for the MMU status to indicate there is no active command, in
> * case one is pending.
> */
> - ret = gpu_read_relaxed_poll_timeout_atomic(ptdev, AS_STATUS(as_nr), val,
> - !(val & AS_STATUS_AS_ACTIVE),
> - 10, 100000);
> + ret = gpu_read_relaxed_poll_timeout_atomic(ptdev->iomem, AS_STATUS(as_nr), val,
> + !(val & AS_STATUS_AS_ACTIVE), 10, 100000);
>
> if (ret) {
> panthor_device_schedule_reset(ptdev);
> @@ -541,7 +540,7 @@ static int as_send_cmd_and_wait(struct panthor_device *ptdev, u32 as_nr, u32 cmd
> /* write AS_COMMAND when MMU is ready to accept another command */
> status = wait_ready(ptdev, as_nr);
> if (!status) {
> - gpu_write(ptdev, AS_COMMAND(as_nr), cmd);
> + gpu_write(ptdev->iomem, AS_COMMAND(as_nr), cmd);
> status = wait_ready(ptdev, as_nr);
> }
>
> @@ -592,9 +591,9 @@ static int panthor_mmu_as_enable(struct panthor_device *ptdev, u32 as_nr,
> panthor_mmu_irq_enable_events(&ptdev->mmu->irq,
> panthor_mmu_as_fault_mask(ptdev, as_nr));
>
> - gpu_write64(ptdev, AS_TRANSTAB(as_nr), transtab);
> - gpu_write64(ptdev, AS_MEMATTR(as_nr), memattr);
> - gpu_write64(ptdev, AS_TRANSCFG(as_nr), transcfg);
> + gpu_write64(ptdev->iomem, AS_TRANSTAB(as_nr), transtab);
> + gpu_write64(ptdev->iomem, AS_MEMATTR(as_nr), memattr);
> + gpu_write64(ptdev->iomem, AS_TRANSCFG(as_nr), transcfg);
>
> return as_send_cmd_and_wait(ptdev, as_nr, AS_COMMAND_UPDATE);
> }
> @@ -629,9 +628,9 @@ static int panthor_mmu_as_disable(struct panthor_device *ptdev, u32 as_nr,
> if (recycle_slot)
> return 0;
>
> - gpu_write64(ptdev, AS_TRANSTAB(as_nr), 0);
> - gpu_write64(ptdev, AS_MEMATTR(as_nr), 0);
> - gpu_write64(ptdev, AS_TRANSCFG(as_nr), AS_TRANSCFG_ADRMODE_UNMAPPED);
> + gpu_write64(ptdev->iomem, AS_TRANSTAB(as_nr), 0);
> + gpu_write64(ptdev->iomem, AS_MEMATTR(as_nr), 0);
> + gpu_write64(ptdev->iomem, AS_TRANSCFG(as_nr), AS_TRANSCFG_ADRMODE_UNMAPPED);
>
> return as_send_cmd_and_wait(ptdev, as_nr, AS_COMMAND_UPDATE);
> }
> @@ -784,7 +783,7 @@ int panthor_vm_active(struct panthor_vm *vm)
> */
> fault_mask = panthor_mmu_as_fault_mask(ptdev, as);
> if (ptdev->mmu->as.faulty_mask & fault_mask) {
> - gpu_write(ptdev, MMU_INT_CLEAR, fault_mask);
> + gpu_write(ptdev->iomem, MMU_INT_CLEAR, fault_mask);
> ptdev->mmu->as.faulty_mask &= ~fault_mask;
> }
>
> @@ -1712,7 +1711,7 @@ static int panthor_vm_lock_region(struct panthor_vm *vm, u64 start, u64 size)
> mutex_lock(&ptdev->mmu->as.slots_lock);
> if (vm->as.id >= 0 && size) {
> /* Lock the region that needs to be updated */
> - gpu_write64(ptdev, AS_LOCKADDR(vm->as.id),
> + gpu_write64(ptdev->iomem, AS_LOCKADDR(vm->as.id),
> pack_region_range(ptdev, &start, &size));
>
> /* If the lock succeeded, update the locked_region info. */
> @@ -1773,8 +1772,8 @@ static void panthor_mmu_irq_handler(struct panthor_device *ptdev, u32 status)
> u32 access_type;
> u32 source_id;
>
> - fault_status = gpu_read(ptdev, AS_FAULTSTATUS(as));
> - addr = gpu_read64(ptdev, AS_FAULTADDRESS(as));
> + fault_status = gpu_read(ptdev->iomem, AS_FAULTSTATUS(as));
> + addr = gpu_read64(ptdev->iomem, AS_FAULTADDRESS(as));
>
> /* decode the fault status */
> exception_type = fault_status & 0xFF;
> @@ -1805,7 +1804,7 @@ static void panthor_mmu_irq_handler(struct panthor_device *ptdev, u32 status)
> * Note that COMPLETED irqs are never cleared, but this is fine
> * because they are always masked.
> */
> - gpu_write(ptdev, MMU_INT_CLEAR, mask);
> + gpu_write(ptdev->iomem, MMU_INT_CLEAR, mask);
>
> if (ptdev->mmu->as.slots[as].vm)
> ptdev->mmu->as.slots[as].vm->unhandled_fault = true;
> diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/panthor/panthor_pwr.c
> index ed3b2b4479ca..b77c85ad733a 100644
> --- a/drivers/gpu/drm/panthor/panthor_pwr.c
> +++ b/drivers/gpu/drm/panthor/panthor_pwr.c
> @@ -55,7 +55,7 @@ struct panthor_pwr {
> static void panthor_pwr_irq_handler(struct panthor_device *ptdev, u32 status)
> {
> spin_lock(&ptdev->pwr->reqs_lock);
> - gpu_write(ptdev, PWR_INT_CLEAR, status);
> + gpu_write(ptdev->iomem, PWR_INT_CLEAR, status);
>
> if (unlikely(status & PWR_IRQ_COMMAND_NOT_ALLOWED))
> drm_err(&ptdev->base, "PWR_IRQ: COMMAND_NOT_ALLOWED");
> @@ -74,14 +74,14 @@ PANTHOR_IRQ_HANDLER(pwr, PWR, panthor_pwr_irq_handler);
> static void panthor_pwr_write_command(struct panthor_device *ptdev, u32 command, u64 args)
> {
> if (args)
> - gpu_write64(ptdev, PWR_CMDARG, args);
> + gpu_write64(ptdev->iomem, PWR_CMDARG, args);
>
> - gpu_write(ptdev, PWR_COMMAND, command);
> + gpu_write(ptdev->iomem, PWR_COMMAND, command);
> }
>
> static bool reset_irq_raised(struct panthor_device *ptdev)
> {
> - return gpu_read(ptdev, PWR_INT_RAWSTAT) & PWR_IRQ_RESET_COMPLETED;
> + return gpu_read(ptdev->iomem, PWR_INT_RAWSTAT) & PWR_IRQ_RESET_COMPLETED;
> }
>
> static bool reset_pending(struct panthor_device *ptdev)
> @@ -96,7 +96,7 @@ static int panthor_pwr_reset(struct panthor_device *ptdev, u32 reset_cmd)
> drm_WARN(&ptdev->base, 1, "Reset already pending");
> } else {
> ptdev->pwr->pending_reqs |= PWR_IRQ_RESET_COMPLETED;
> - gpu_write(ptdev, PWR_INT_CLEAR, PWR_IRQ_RESET_COMPLETED);
> + gpu_write(ptdev->iomem, PWR_INT_CLEAR, PWR_IRQ_RESET_COMPLETED);
> panthor_pwr_write_command(ptdev, reset_cmd, 0);
> }
> }
> @@ -185,7 +185,7 @@ static int panthor_pwr_domain_wait_transition(struct panthor_device *ptdev, u32
> u64 val;
> int ret = 0;
>
> - ret = gpu_read64_poll_timeout(ptdev, pwrtrans_reg, val, !(PWR_ALL_CORES_MASK & val), 100,
> + ret = gpu_read64_poll_timeout(ptdev->iomem, pwrtrans_reg, val, !(PWR_ALL_CORES_MASK & val), 100,
> timeout_us);
> if (ret) {
> drm_err(&ptdev->base, "%s domain power in transition, pwrtrans(0x%llx)",
> @@ -198,17 +198,17 @@ static int panthor_pwr_domain_wait_transition(struct panthor_device *ptdev, u32
>
> static void panthor_pwr_debug_info_show(struct panthor_device *ptdev)
> {
> - drm_info(&ptdev->base, "GPU_FEATURES: 0x%016llx", gpu_read64(ptdev, GPU_FEATURES));
> - drm_info(&ptdev->base, "PWR_STATUS: 0x%016llx", gpu_read64(ptdev, PWR_STATUS));
> - drm_info(&ptdev->base, "L2_PRESENT: 0x%016llx", gpu_read64(ptdev, PWR_L2_PRESENT));
> - drm_info(&ptdev->base, "L2_PWRTRANS: 0x%016llx", gpu_read64(ptdev, PWR_L2_PWRTRANS));
> - drm_info(&ptdev->base, "L2_READY: 0x%016llx", gpu_read64(ptdev, PWR_L2_READY));
> - drm_info(&ptdev->base, "TILER_PRESENT: 0x%016llx", gpu_read64(ptdev, PWR_TILER_PRESENT));
> - drm_info(&ptdev->base, "TILER_PWRTRANS: 0x%016llx", gpu_read64(ptdev, PWR_TILER_PWRTRANS));
> - drm_info(&ptdev->base, "TILER_READY: 0x%016llx", gpu_read64(ptdev, PWR_TILER_READY));
> - drm_info(&ptdev->base, "SHADER_PRESENT: 0x%016llx", gpu_read64(ptdev, PWR_SHADER_PRESENT));
> - drm_info(&ptdev->base, "SHADER_PWRTRANS: 0x%016llx", gpu_read64(ptdev, PWR_SHADER_PWRTRANS));
> - drm_info(&ptdev->base, "SHADER_READY: 0x%016llx", gpu_read64(ptdev, PWR_SHADER_READY));
> + drm_info(&ptdev->base, "GPU_FEATURES: 0x%016llx", gpu_read64(ptdev->iomem, GPU_FEATURES));
> + drm_info(&ptdev->base, "PWR_STATUS: 0x%016llx", gpu_read64(ptdev->iomem, PWR_STATUS));
> + drm_info(&ptdev->base, "L2_PRESENT: 0x%016llx", gpu_read64(ptdev->iomem, PWR_L2_PRESENT));
> + drm_info(&ptdev->base, "L2_PWRTRANS: 0x%016llx", gpu_read64(ptdev->iomem, PWR_L2_PWRTRANS));
> + drm_info(&ptdev->base, "L2_READY: 0x%016llx", gpu_read64(ptdev->iomem, PWR_L2_READY));
> + drm_info(&ptdev->base, "TILER_PRESENT: 0x%016llx", gpu_read64(ptdev->iomem, PWR_TILER_PRESENT));
> + drm_info(&ptdev->base, "TILER_PWRTRANS: 0x%016llx", gpu_read64(ptdev->iomem, PWR_TILER_PWRTRANS));
> + drm_info(&ptdev->base, "TILER_READY: 0x%016llx", gpu_read64(ptdev->iomem, PWR_TILER_READY));
> + drm_info(&ptdev->base, "SHADER_PRESENT: 0x%016llx", gpu_read64(ptdev->iomem, PWR_SHADER_PRESENT));
> + drm_info(&ptdev->base, "SHADER_PWRTRANS: 0x%016llx", gpu_read64(ptdev->iomem, PWR_SHADER_PWRTRANS));
> + drm_info(&ptdev->base, "SHADER_READY: 0x%016llx", gpu_read64(ptdev->iomem, PWR_SHADER_READY));
> }
>
> static int panthor_pwr_domain_transition(struct panthor_device *ptdev, u32 cmd, u32 domain,
> @@ -240,13 +240,13 @@ static int panthor_pwr_domain_transition(struct panthor_device *ptdev, u32 cmd,
> return ret;
>
> /* domain already in target state, return early */
> - if ((gpu_read64(ptdev, ready_reg) & mask) == expected_val)
> + if ((gpu_read64(ptdev->iomem, ready_reg) & mask) == expected_val)
> return 0;
>
> panthor_pwr_write_command(ptdev, pwr_cmd, mask);
>
> - ret = gpu_read64_poll_timeout(ptdev, ready_reg, val, (mask & val) == expected_val, 100,
> - timeout_us);
> + ret = gpu_read64_poll_timeout(ptdev->iomem, ready_reg, val, (mask & val) == expected_val,
> + 100, timeout_us);
> if (ret) {
> drm_err(&ptdev->base,
> "timeout waiting on %s power domain transition, cmd(0x%x), arg(0x%llx)",
> @@ -279,7 +279,7 @@ static int panthor_pwr_domain_transition(struct panthor_device *ptdev, u32 cmd,
> static int retract_domain(struct panthor_device *ptdev, u32 domain)
> {
> const u32 pwr_cmd = PWR_COMMAND_DEF(PWR_COMMAND_RETRACT, domain, 0);
> - const u64 pwr_status = gpu_read64(ptdev, PWR_STATUS);
> + const u64 pwr_status = gpu_read64(ptdev->iomem, PWR_STATUS);
> const u64 delegated_mask = PWR_STATUS_DOMAIN_DELEGATED(domain);
> const u64 allow_mask = PWR_STATUS_DOMAIN_ALLOWED(domain);
> u64 val;
> @@ -288,8 +288,9 @@ static int retract_domain(struct panthor_device *ptdev, u32 domain)
> if (drm_WARN_ON(&ptdev->base, domain == PWR_COMMAND_DOMAIN_L2))
> return -EPERM;
>
> - ret = gpu_read64_poll_timeout(ptdev, PWR_STATUS, val, !(PWR_STATUS_RETRACT_PENDING & val),
> - 0, PWR_RETRACT_TIMEOUT_US);
> + ret = gpu_read64_poll_timeout(ptdev->iomem, PWR_STATUS, val,
> + !(PWR_STATUS_RETRACT_PENDING & val), 0,
> + PWR_RETRACT_TIMEOUT_US);
> if (ret) {
> drm_err(&ptdev->base, "%s domain retract pending", get_domain_name(domain));
> return ret;
> @@ -306,7 +307,7 @@ static int retract_domain(struct panthor_device *ptdev, u32 domain)
> * On successful retraction
> * allow-flag will be set with delegated-flag being cleared.
> */
> - ret = gpu_read64_poll_timeout(ptdev, PWR_STATUS, val,
> + ret = gpu_read64_poll_timeout(ptdev->iomem, PWR_STATUS, val,
> ((delegated_mask | allow_mask) & val) == allow_mask, 10,
> PWR_TRANSITION_TIMEOUT_US);
> if (ret) {
> @@ -333,7 +334,7 @@ static int retract_domain(struct panthor_device *ptdev, u32 domain)
> static int delegate_domain(struct panthor_device *ptdev, u32 domain)
> {
> const u32 pwr_cmd = PWR_COMMAND_DEF(PWR_COMMAND_DELEGATE, domain, 0);
> - const u64 pwr_status = gpu_read64(ptdev, PWR_STATUS);
> + const u64 pwr_status = gpu_read64(ptdev->iomem, PWR_STATUS);
> const u64 allow_mask = PWR_STATUS_DOMAIN_ALLOWED(domain);
> const u64 delegated_mask = PWR_STATUS_DOMAIN_DELEGATED(domain);
> u64 val;
> @@ -362,7 +363,7 @@ static int delegate_domain(struct panthor_device *ptdev, u32 domain)
> * On successful delegation
> * allow-flag will be cleared with delegated-flag being set.
> */
> - ret = gpu_read64_poll_timeout(ptdev, PWR_STATUS, val,
> + ret = gpu_read64_poll_timeout(ptdev->iomem, PWR_STATUS, val,
> ((delegated_mask | allow_mask) & val) == delegated_mask,
> 10, PWR_TRANSITION_TIMEOUT_US);
> if (ret) {
> @@ -410,7 +411,7 @@ static int panthor_pwr_delegate_domains(struct panthor_device *ptdev)
> */
> static int panthor_pwr_domain_force_off(struct panthor_device *ptdev, u32 domain)
> {
> - const u64 domain_ready = gpu_read64(ptdev, get_domain_ready_reg(domain));
> + const u64 domain_ready = gpu_read64(ptdev->iomem, get_domain_ready_reg(domain));
> int ret;
>
> /* Domain already powered down, early exit. */
> @@ -471,7 +472,7 @@ int panthor_pwr_init(struct panthor_device *ptdev)
>
> int panthor_pwr_reset_soft(struct panthor_device *ptdev)
> {
> - if (!(gpu_read64(ptdev, PWR_STATUS) & PWR_STATUS_ALLOW_SOFT_RESET)) {
> + if (!(gpu_read64(ptdev->iomem, PWR_STATUS) & PWR_STATUS_ALLOW_SOFT_RESET)) {
> drm_err(&ptdev->base, "RESET_SOFT not allowed");
> return -EOPNOTSUPP;
> }
> @@ -482,7 +483,7 @@ int panthor_pwr_reset_soft(struct panthor_device *ptdev)
> void panthor_pwr_l2_power_off(struct panthor_device *ptdev)
> {
> const u64 l2_allow_mask = PWR_STATUS_DOMAIN_ALLOWED(PWR_COMMAND_DOMAIN_L2);
> - const u64 pwr_status = gpu_read64(ptdev, PWR_STATUS);
> + const u64 pwr_status = gpu_read64(ptdev->iomem, PWR_STATUS);
>
> /* Abort if L2 power off constraints are not satisfied */
> if (!(pwr_status & l2_allow_mask)) {
> @@ -508,7 +509,7 @@ void panthor_pwr_l2_power_off(struct panthor_device *ptdev)
>
> int panthor_pwr_l2_power_on(struct panthor_device *ptdev)
> {
> - const u32 pwr_status = gpu_read64(ptdev, PWR_STATUS);
> + const u32 pwr_status = gpu_read64(ptdev->iomem, PWR_STATUS);
> const u32 l2_allow_mask = PWR_STATUS_DOMAIN_ALLOWED(PWR_COMMAND_DOMAIN_L2);
> int ret;
>
> diff --git a/drivers/gpu/drm/panthor/panthor_sched.c b/drivers/gpu/drm/panthor/panthor_sched.c
> index a06d91875beb..7c8d350da02f 100644
> --- a/drivers/gpu/drm/panthor/panthor_sched.c
> +++ b/drivers/gpu/drm/panthor/panthor_sched.c
> @@ -3372,7 +3372,7 @@ queue_run_job(struct drm_sched_job *sched_job)
> if (resume_tick)
> sched_resume_tick(ptdev);
>
> - gpu_write(ptdev, CSF_DOORBELL(queue->doorbell_id), 1);
> + gpu_write(ptdev->iomem, CSF_DOORBELL(queue->doorbell_id), 1);
> if (!sched->pm.has_ref &&
> !(group->blocked_queues & BIT(job->queue_idx))) {
> pm_runtime_get(ptdev->base.dev);
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/8] drm/panthor: Split register definitions by components
2026-04-10 16:46 [PATCH 0/8] drm/panthor: Localize register access by component Karunika Choo
2026-04-10 16:46 ` [PATCH 1/8] drm/panthor: Pass an iomem pointer to GPU register access helpers Karunika Choo
@ 2026-04-10 16:46 ` Karunika Choo
2026-04-10 18:08 ` Boris Brezillon
2026-04-10 16:46 ` [PATCH 3/8] drm/panthor: Replace cross-component register accesses with helpers Karunika Choo
` (5 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Karunika Choo @ 2026-04-10 16:46 UTC (permalink / raw)
To: dri-devel
Cc: nd, Boris Brezillon, Steven Price, Liviu Dudau, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
linux-kernel
Split the panthor register definitions into per-component headers for
the GPU, MMU, firmware, power and generic hardware registers.
This makes the register layout easier to follow and prepares the driver
for component-local iomem mappings by grouping definitions with the code
that owns them. The old monolithic panthor_regs.h header can then be
dropped.
No functional change intended.
Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
drivers/gpu/drm/panthor/panthor_device.c | 3 +-
drivers/gpu/drm/panthor/panthor_drv.c | 2 +-
drivers/gpu/drm/panthor/panthor_fw.c | 2 +-
drivers/gpu/drm/panthor/panthor_fw_regs.h | 30 +++
drivers/gpu/drm/panthor/panthor_gpu.c | 2 +-
drivers/gpu/drm/panthor/panthor_gpu_regs.h | 111 ++++++++
drivers/gpu/drm/panthor/panthor_heap.c | 2 +-
drivers/gpu/drm/panthor/panthor_hw.c | 3 +-
drivers/gpu/drm/panthor/panthor_hw.h | 2 +-
drivers/gpu/drm/panthor/panthor_hw_regs.h | 16 ++
drivers/gpu/drm/panthor/panthor_mmu.c | 3 +-
drivers/gpu/drm/panthor/panthor_mmu_regs.h | 70 +++++
drivers/gpu/drm/panthor/panthor_pwr.c | 3 +-
drivers/gpu/drm/panthor/panthor_pwr_regs.h | 83 ++++++
drivers/gpu/drm/panthor/panthor_regs.h | 291 ---------------------
drivers/gpu/drm/panthor/panthor_sched.c | 3 +-
16 files changed, 325 insertions(+), 301 deletions(-)
create mode 100644 drivers/gpu/drm/panthor/panthor_fw_regs.h
create mode 100644 drivers/gpu/drm/panthor/panthor_gpu_regs.h
create mode 100644 drivers/gpu/drm/panthor/panthor_hw_regs.h
create mode 100644 drivers/gpu/drm/panthor/panthor_mmu_regs.h
create mode 100644 drivers/gpu/drm/panthor/panthor_pwr_regs.h
delete mode 100644 drivers/gpu/drm/panthor/panthor_regs.h
diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/panthor/panthor_device.c
index d62017b73409..f876b13492ae 100644
--- a/drivers/gpu/drm/panthor/panthor_device.c
+++ b/drivers/gpu/drm/panthor/panthor_device.c
@@ -19,12 +19,13 @@
#include "panthor_devfreq.h"
#include "panthor_device.h"
#include "panthor_fw.h"
+#include "panthor_fw_regs.h"
#include "panthor_gem.h"
#include "panthor_gpu.h"
+#include "panthor_gpu_regs.h"
#include "panthor_hw.h"
#include "panthor_mmu.h"
#include "panthor_pwr.h"
-#include "panthor_regs.h"
#include "panthor_sched.h"
static int panthor_gpu_coherency_init(struct panthor_device *ptdev)
diff --git a/drivers/gpu/drm/panthor/panthor_drv.c b/drivers/gpu/drm/panthor/panthor_drv.c
index 4f926c861fba..e63210b01e6e 100644
--- a/drivers/gpu/drm/panthor/panthor_drv.c
+++ b/drivers/gpu/drm/panthor/panthor_drv.c
@@ -34,9 +34,9 @@
#include "panthor_fw.h"
#include "panthor_gem.h"
#include "panthor_gpu.h"
+#include "panthor_gpu_regs.h"
#include "panthor_heap.h"
#include "panthor_mmu.h"
-#include "panthor_regs.h"
#include "panthor_sched.h"
/**
diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor/panthor_fw.c
index 69a19751a314..4704275b9c8f 100644
--- a/drivers/gpu/drm/panthor/panthor_fw.c
+++ b/drivers/gpu/drm/panthor/panthor_fw.c
@@ -20,11 +20,11 @@
#include "panthor_device.h"
#include "panthor_fw.h"
+#include "panthor_fw_regs.h"
#include "panthor_gem.h"
#include "panthor_gpu.h"
#include "panthor_hw.h"
#include "panthor_mmu.h"
-#include "panthor_regs.h"
#include "panthor_sched.h"
#include "panthor_trace.h"
diff --git a/drivers/gpu/drm/panthor/panthor_fw_regs.h b/drivers/gpu/drm/panthor/panthor_fw_regs.h
new file mode 100644
index 000000000000..d523d41e18dd
--- /dev/null
+++ b/drivers/gpu/drm/panthor/panthor_fw_regs.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 or MIT */
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#ifndef __PANTHOR_FW_REGS_H__
+#define __PANTHOR_FW_REGS_H__
+
+#define MCU_CONTROL 0x700
+#define MCU_CONTROL_ENABLE 1
+#define MCU_CONTROL_AUTO 2
+#define MCU_CONTROL_DISABLE 0
+
+#define MCU_STATUS 0x704
+#define MCU_STATUS_DISABLED 0
+#define MCU_STATUS_ENABLED 1
+#define MCU_STATUS_HALT 2
+#define MCU_STATUS_FATAL 3
+
+#define JOB_INT_RAWSTAT 0x1000
+#define JOB_INT_CLEAR 0x1004
+#define JOB_INT_MASK 0x1008
+#define JOB_INT_STAT 0x100c
+#define JOB_INT_GLOBAL_IF BIT(31)
+#define JOB_INT_CSG_IF(x) BIT(x)
+
+#define CSF_GPU_LATEST_FLUSH_ID 0x10000
+
+#define CSF_DOORBELL(i) (0x80000 + ((i) * 0x10000))
+#define CSF_GLB_DOORBELL_ID 0
+
+#endif /* __PANTHOR_FW_REGS_H__ */
diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c
index bdb72cebccb3..fecc30747acf 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu.c
+++ b/drivers/gpu/drm/panthor/panthor_gpu.c
@@ -19,8 +19,8 @@
#include "panthor_device.h"
#include "panthor_gpu.h"
+#include "panthor_gpu_regs.h"
#include "panthor_hw.h"
-#include "panthor_regs.h"
#define CREATE_TRACE_POINTS
#include "panthor_trace.h"
diff --git a/drivers/gpu/drm/panthor/panthor_gpu_regs.h b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
new file mode 100644
index 000000000000..7303b7f5ee18
--- /dev/null
+++ b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0 or MIT */
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#ifndef __PANTHOR_GPU_REGS_H__
+#define __PANTHOR_GPU_REGS_H__
+
+#define GPU_L2_FEATURES 0x4
+#define GPU_L2_FEATURES_LINE_SIZE(x) (1 << ((x) & GENMASK(7, 0)))
+
+#define GPU_CORE_FEATURES 0x8
+
+#define GPU_TILER_FEATURES 0xC
+#define GPU_MEM_FEATURES 0x10
+#define GROUPS_L2_COHERENT BIT(0)
+
+#define GPU_MMU_FEATURES 0x14
+#define GPU_MMU_FEATURES_VA_BITS(x) ((x) & GENMASK(7, 0))
+#define GPU_MMU_FEATURES_PA_BITS(x) (((x) >> 8) & GENMASK(7, 0))
+#define GPU_AS_PRESENT 0x18
+#define GPU_CSF_ID 0x1C
+
+#define GPU_INT_RAWSTAT 0x20
+#define GPU_INT_CLEAR 0x24
+#define GPU_INT_MASK 0x28
+#define GPU_INT_STAT 0x2c
+#define GPU_IRQ_FAULT BIT(0)
+#define GPU_IRQ_PROTM_FAULT BIT(1)
+#define GPU_IRQ_RESET_COMPLETED BIT(8)
+#define GPU_IRQ_POWER_CHANGED BIT(9)
+#define GPU_IRQ_POWER_CHANGED_ALL BIT(10)
+#define GPU_IRQ_CLEAN_CACHES_COMPLETED BIT(17)
+#define GPU_IRQ_DOORBELL_MIRROR BIT(18)
+#define GPU_IRQ_MCU_STATUS_CHANGED BIT(19)
+#define GPU_CMD 0x30
+#define GPU_CMD_DEF(type, payload) ((type) | ((payload) << 8))
+#define GPU_SOFT_RESET GPU_CMD_DEF(1, 1)
+#define GPU_HARD_RESET GPU_CMD_DEF(1, 2)
+#define CACHE_CLEAN BIT(0)
+#define CACHE_INV BIT(1)
+#define GPU_FLUSH_CACHES(l2, lsc, oth) \
+ GPU_CMD_DEF(4, ((l2) << 0) | ((lsc) << 4) | ((oth) << 8))
+
+#define GPU_STATUS 0x34
+#define GPU_STATUS_ACTIVE BIT(0)
+#define GPU_STATUS_PWR_ACTIVE BIT(1)
+#define GPU_STATUS_PAGE_FAULT BIT(4)
+#define GPU_STATUS_PROTM_ACTIVE BIT(7)
+#define GPU_STATUS_DBG_ENABLED BIT(8)
+
+#define GPU_FAULT_STATUS 0x3C
+#define GPU_FAULT_ADDR 0x40
+#define GPU_L2_CONFIG 0x48
+#define GPU_L2_CONFIG_ASN_HASH_ENABLE BIT(24)
+
+#define GPU_PWR_KEY 0x50
+#define GPU_PWR_KEY_UNLOCK 0x2968A819
+#define GPU_PWR_OVERRIDE0 0x54
+#define GPU_PWR_OVERRIDE1 0x58
+
+#define GPU_FEATURES 0x60
+#define GPU_FEATURES_RAY_INTERSECTION BIT(2)
+#define GPU_FEATURES_RAY_TRAVERSAL BIT(5)
+
+#define GPU_TIMESTAMP_OFFSET 0x88
+#define GPU_CYCLE_COUNT 0x90
+#define GPU_TIMESTAMP 0x98
+
+#define GPU_THREAD_MAX_THREADS 0xA0
+#define GPU_THREAD_MAX_WORKGROUP_SIZE 0xA4
+#define GPU_THREAD_MAX_BARRIER_SIZE 0xA8
+#define GPU_THREAD_FEATURES 0xAC
+
+#define GPU_TEXTURE_FEATURES(n) (0xB0 + ((n) * 4))
+
+#define GPU_SHADER_PRESENT 0x100
+#define GPU_TILER_PRESENT 0x110
+#define GPU_L2_PRESENT 0x120
+
+#define SHADER_READY 0x140
+#define TILER_READY 0x150
+#define L2_READY 0x160
+
+#define SHADER_PWRON 0x180
+#define TILER_PWRON 0x190
+#define L2_PWRON 0x1A0
+
+#define SHADER_PWROFF 0x1C0
+#define TILER_PWROFF 0x1D0
+#define L2_PWROFF 0x1E0
+
+#define SHADER_PWRTRANS 0x200
+#define TILER_PWRTRANS 0x210
+#define L2_PWRTRANS 0x220
+
+#define SHADER_PWRACTIVE 0x240
+#define TILER_PWRACTIVE 0x250
+#define L2_PWRACTIVE 0x260
+
+#define GPU_REVID 0x280
+
+#define GPU_ASN_HASH(n) (0x2C0 + ((n) * 4))
+
+#define GPU_COHERENCY_FEATURES 0x300
+#define GPU_COHERENCY_PROT_BIT(name) BIT(GPU_COHERENCY_ ## name)
+
+#define GPU_COHERENCY_PROTOCOL 0x304
+#define GPU_COHERENCY_ACE_LITE 0
+#define GPU_COHERENCY_ACE 1
+#define GPU_COHERENCY_NONE 31
+
+#endif /* __PANTHOR_GPU_REGS_H__ */
diff --git a/drivers/gpu/drm/panthor/panthor_heap.c b/drivers/gpu/drm/panthor/panthor_heap.c
index 1ee30dc7066f..99311abdf1e9 100644
--- a/drivers/gpu/drm/panthor/panthor_heap.c
+++ b/drivers/gpu/drm/panthor/panthor_heap.c
@@ -9,9 +9,9 @@
#include "panthor_device.h"
#include "panthor_gem.h"
+#include "panthor_gpu_regs.h"
#include "panthor_heap.h"
#include "panthor_mmu.h"
-#include "panthor_regs.h"
/*
* The GPU heap context is an opaque structure used by the GPU to track the
diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor/panthor_hw.c
index 9309d0938212..9431f16d950f 100644
--- a/drivers/gpu/drm/panthor/panthor_hw.c
+++ b/drivers/gpu/drm/panthor/panthor_hw.c
@@ -8,9 +8,10 @@
#include "panthor_device.h"
#include "panthor_gpu.h"
+#include "panthor_gpu_regs.h"
#include "panthor_hw.h"
#include "panthor_pwr.h"
-#include "panthor_regs.h"
+#include "panthor_pwr_regs.h"
#define GPU_PROD_ID_MAKE(arch_major, prod_major) \
(((arch_major) << 24) | (prod_major))
diff --git a/drivers/gpu/drm/panthor/panthor_hw.h b/drivers/gpu/drm/panthor/panthor_hw.h
index 2c28aea82841..7f134c4b290f 100644
--- a/drivers/gpu/drm/panthor/panthor_hw.h
+++ b/drivers/gpu/drm/panthor/panthor_hw.h
@@ -5,7 +5,7 @@
#define __PANTHOR_HW_H__
#include "panthor_device.h"
-#include "panthor_regs.h"
+#include "panthor_hw_regs.h"
/**
* struct panthor_hw_ops - HW operations that are specific to a GPU
diff --git a/drivers/gpu/drm/panthor/panthor_hw_regs.h b/drivers/gpu/drm/panthor/panthor_hw_regs.h
new file mode 100644
index 000000000000..6295374a69ab
--- /dev/null
+++ b/drivers/gpu/drm/panthor/panthor_hw_regs.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 or MIT */
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#ifndef __PANTHOR_HW_REGS_H__
+#define __PANTHOR_HW_REGS_H__
+
+#define GPU_ID 0x0
+#define GPU_ARCH_MAJOR(x) ((x) >> 28)
+#define GPU_ARCH_MINOR(x) (((x) & GENMASK(27, 24)) >> 24)
+#define GPU_ARCH_REV(x) (((x) & GENMASK(23, 20)) >> 20)
+#define GPU_PROD_MAJOR(x) (((x) & GENMASK(19, 16)) >> 16)
+#define GPU_VER_MAJOR(x) (((x) & GENMASK(15, 12)) >> 12)
+#define GPU_VER_MINOR(x) (((x) & GENMASK(11, 4)) >> 4)
+#define GPU_VER_STATUS(x) ((x) & GENMASK(3, 0))
+
+#endif /* __PANTHOR_HW_REGS_H__ */
diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c b/drivers/gpu/drm/panthor/panthor_mmu.c
index 0bd07a3dd774..b9f6031e24a4 100644
--- a/drivers/gpu/drm/panthor/panthor_mmu.c
+++ b/drivers/gpu/drm/panthor/panthor_mmu.c
@@ -33,9 +33,10 @@
#include "panthor_device.h"
#include "panthor_gem.h"
#include "panthor_gpu.h"
+#include "panthor_gpu_regs.h"
#include "panthor_heap.h"
#include "panthor_mmu.h"
-#include "panthor_regs.h"
+#include "panthor_mmu_regs.h"
#include "panthor_sched.h"
#define MAX_AS_SLOTS 32
diff --git a/drivers/gpu/drm/panthor/panthor_mmu_regs.h b/drivers/gpu/drm/panthor/panthor_mmu_regs.h
new file mode 100644
index 000000000000..cc9cf603cec6
--- /dev/null
+++ b/drivers/gpu/drm/panthor/panthor_mmu_regs.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0 or MIT */
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#ifndef __PANTHOR_MMU_REGS_H__
+#define __PANTHOR_MMU_REGS_H__
+
+/* MMU regs */
+#define MMU_INT_RAWSTAT 0x2000
+#define MMU_INT_CLEAR 0x2004
+#define MMU_INT_MASK 0x2008
+#define MMU_INT_STAT 0x200c
+
+/* AS_COMMAND register commands */
+
+#define MMU_BASE 0x2400
+#define MMU_AS_SHIFT 6
+#define MMU_AS(as) (MMU_BASE + ((as) << MMU_AS_SHIFT))
+
+#define AS_TRANSTAB(as) (MMU_AS(as) + 0x0)
+#define AS_MEMATTR(as) (MMU_AS(as) + 0x8)
+#define AS_MEMATTR_AARCH64_INNER_ALLOC_IMPL (2 << 2)
+#define AS_MEMATTR_AARCH64_INNER_ALLOC_EXPL(w, r) ((3 << 2) | \
+ ((w) ? BIT(0) : 0) | \
+ ((r) ? BIT(1) : 0))
+#define AS_MEMATTR_AARCH64_SH_MIDGARD_INNER (0 << 4)
+#define AS_MEMATTR_AARCH64_SH_CPU_INNER (1 << 4)
+#define AS_MEMATTR_AARCH64_SH_CPU_INNER_SHADER_COH (2 << 4)
+#define AS_MEMATTR_AARCH64_SHARED (0 << 6)
+#define AS_MEMATTR_AARCH64_INNER_OUTER_NC (1 << 6)
+#define AS_MEMATTR_AARCH64_INNER_OUTER_WB (2 << 6)
+#define AS_MEMATTR_AARCH64_FAULT (3 << 6)
+#define AS_LOCKADDR(as) (MMU_AS(as) + 0x10)
+#define AS_COMMAND(as) (MMU_AS(as) + 0x18)
+#define AS_COMMAND_NOP 0
+#define AS_COMMAND_UPDATE 1
+#define AS_COMMAND_LOCK 2
+#define AS_COMMAND_UNLOCK 3
+#define AS_COMMAND_FLUSH_PT 4
+#define AS_COMMAND_FLUSH_MEM 5
+#define AS_LOCK_REGION_MIN_SIZE (1ULL << 15)
+#define AS_FAULTSTATUS(as) (MMU_AS(as) + 0x1C)
+#define AS_FAULTSTATUS_ACCESS_TYPE_MASK (0x3 << 8)
+#define AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC (0x0 << 8)
+#define AS_FAULTSTATUS_ACCESS_TYPE_EX (0x1 << 8)
+#define AS_FAULTSTATUS_ACCESS_TYPE_READ (0x2 << 8)
+#define AS_FAULTSTATUS_ACCESS_TYPE_WRITE (0x3 << 8)
+#define AS_FAULTADDRESS(as) (MMU_AS(as) + 0x20)
+#define AS_STATUS(as) (MMU_AS(as) + 0x28)
+#define AS_STATUS_AS_ACTIVE BIT(0)
+#define AS_TRANSCFG(as) (MMU_AS(as) + 0x30)
+#define AS_TRANSCFG_ADRMODE_UNMAPPED (1 << 0)
+#define AS_TRANSCFG_ADRMODE_IDENTITY (2 << 0)
+#define AS_TRANSCFG_ADRMODE_AARCH64_4K (6 << 0)
+#define AS_TRANSCFG_ADRMODE_AARCH64_64K (8 << 0)
+#define AS_TRANSCFG_INA_BITS(x) ((x) << 6)
+#define AS_TRANSCFG_OUTA_BITS(x) ((x) << 14)
+#define AS_TRANSCFG_SL_CONCAT BIT(22)
+#define AS_TRANSCFG_PTW_MEMATTR_NC (1 << 24)
+#define AS_TRANSCFG_PTW_MEMATTR_WB (2 << 24)
+#define AS_TRANSCFG_PTW_SH_NS (0 << 28)
+#define AS_TRANSCFG_PTW_SH_OS (2 << 28)
+#define AS_TRANSCFG_PTW_SH_IS (3 << 28)
+#define AS_TRANSCFG_PTW_RA BIT(30)
+#define AS_TRANSCFG_DISABLE_HIER_AP BIT(33)
+#define AS_TRANSCFG_DISABLE_AF_FAULT BIT(34)
+#define AS_TRANSCFG_WXN BIT(35)
+#define AS_TRANSCFG_XREADABLE BIT(36)
+#define AS_FAULTEXTRA(as) (MMU_AS(as) + 0x38)
+
+#endif /* __PANTHOR_MMU_REGS_H__ */
diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/panthor/panthor_pwr.c
index b77c85ad733a..306592ff2227 100644
--- a/drivers/gpu/drm/panthor/panthor_pwr.c
+++ b/drivers/gpu/drm/panthor/panthor_pwr.c
@@ -11,9 +11,10 @@
#include <drm/drm_print.h>
#include "panthor_device.h"
+#include "panthor_gpu_regs.h"
#include "panthor_hw.h"
#include "panthor_pwr.h"
-#include "panthor_regs.h"
+#include "panthor_pwr_regs.h"
#define PWR_INTERRUPTS_MASK \
(PWR_IRQ_POWER_CHANGED_SINGLE | \
diff --git a/drivers/gpu/drm/panthor/panthor_pwr_regs.h b/drivers/gpu/drm/panthor/panthor_pwr_regs.h
new file mode 100644
index 000000000000..ad3e446971db
--- /dev/null
+++ b/drivers/gpu/drm/panthor/panthor_pwr_regs.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0 or MIT */
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#ifndef __PANTHOR_PWR_REGS_H__
+#define __PANTHOR_PWR_REGS_H__
+
+#define PWR_CONTROL_BASE 0x800
+#define PWR_CTRL_REG(x) (PWR_CONTROL_BASE + (x))
+
+#define PWR_INT_RAWSTAT PWR_CTRL_REG(0x0)
+#define PWR_INT_CLEAR PWR_CTRL_REG(0x4)
+#define PWR_INT_MASK PWR_CTRL_REG(0x8)
+#define PWR_INT_STAT PWR_CTRL_REG(0xc)
+#define PWR_IRQ_POWER_CHANGED_SINGLE BIT(0)
+#define PWR_IRQ_POWER_CHANGED_ALL BIT(1)
+#define PWR_IRQ_DELEGATION_CHANGED BIT(2)
+#define PWR_IRQ_RESET_COMPLETED BIT(3)
+#define PWR_IRQ_RETRACT_COMPLETED BIT(4)
+#define PWR_IRQ_INSPECT_COMPLETED BIT(5)
+#define PWR_IRQ_COMMAND_NOT_ALLOWED BIT(30)
+#define PWR_IRQ_COMMAND_INVALID BIT(31)
+
+#define PWR_STATUS PWR_CTRL_REG(0x20)
+#define PWR_STATUS_ALLOW_L2 BIT_U64(0)
+#define PWR_STATUS_ALLOW_TILER BIT_U64(1)
+#define PWR_STATUS_ALLOW_SHADER BIT_U64(8)
+#define PWR_STATUS_ALLOW_BASE BIT_U64(14)
+#define PWR_STATUS_ALLOW_STACK BIT_U64(15)
+#define PWR_STATUS_DOMAIN_ALLOWED(x) BIT_U64(x)
+#define PWR_STATUS_DELEGATED_L2 BIT_U64(16)
+#define PWR_STATUS_DELEGATED_TILER BIT_U64(17)
+#define PWR_STATUS_DELEGATED_SHADER BIT_U64(24)
+#define PWR_STATUS_DELEGATED_BASE BIT_U64(30)
+#define PWR_STATUS_DELEGATED_STACK BIT_U64(31)
+#define PWR_STATUS_DELEGATED_SHIFT 16
+#define PWR_STATUS_DOMAIN_DELEGATED(x) BIT_U64((x) + PWR_STATUS_DELEGATED_SHIFT)
+#define PWR_STATUS_ALLOW_SOFT_RESET BIT_U64(33)
+#define PWR_STATUS_ALLOW_FAST_RESET BIT_U64(34)
+#define PWR_STATUS_POWER_PENDING BIT_U64(41)
+#define PWR_STATUS_RESET_PENDING BIT_U64(42)
+#define PWR_STATUS_RETRACT_PENDING BIT_U64(43)
+#define PWR_STATUS_INSPECT_PENDING BIT_U64(44)
+
+#define PWR_COMMAND PWR_CTRL_REG(0x28)
+#define PWR_COMMAND_POWER_UP 0x10
+#define PWR_COMMAND_POWER_DOWN 0x11
+#define PWR_COMMAND_DELEGATE 0x20
+#define PWR_COMMAND_RETRACT 0x21
+#define PWR_COMMAND_RESET_SOFT 0x31
+#define PWR_COMMAND_RESET_FAST 0x32
+#define PWR_COMMAND_INSPECT 0xF0
+#define PWR_COMMAND_DOMAIN_L2 0
+#define PWR_COMMAND_DOMAIN_TILER 1
+#define PWR_COMMAND_DOMAIN_SHADER 8
+#define PWR_COMMAND_DOMAIN_BASE 14
+#define PWR_COMMAND_DOMAIN_STACK 15
+#define PWR_COMMAND_SUBDOMAIN_RTU BIT(0)
+#define PWR_COMMAND_DEF(cmd, domain, subdomain) \
+ (((subdomain) << 16) | ((domain) << 8) | (cmd))
+
+#define PWR_CMDARG PWR_CTRL_REG(0x30)
+
+#define PWR_L2_PRESENT PWR_CTRL_REG(0x100)
+#define PWR_L2_READY PWR_CTRL_REG(0x108)
+#define PWR_L2_PWRTRANS PWR_CTRL_REG(0x110)
+#define PWR_L2_PWRACTIVE PWR_CTRL_REG(0x118)
+#define PWR_TILER_PRESENT PWR_CTRL_REG(0x140)
+#define PWR_TILER_READY PWR_CTRL_REG(0x148)
+#define PWR_TILER_PWRTRANS PWR_CTRL_REG(0x150)
+#define PWR_TILER_PWRACTIVE PWR_CTRL_REG(0x158)
+#define PWR_SHADER_PRESENT PWR_CTRL_REG(0x200)
+#define PWR_SHADER_READY PWR_CTRL_REG(0x208)
+#define PWR_SHADER_PWRTRANS PWR_CTRL_REG(0x210)
+#define PWR_SHADER_PWRACTIVE PWR_CTRL_REG(0x218)
+#define PWR_BASE_PRESENT PWR_CTRL_REG(0x380)
+#define PWR_BASE_READY PWR_CTRL_REG(0x388)
+#define PWR_BASE_PWRTRANS PWR_CTRL_REG(0x390)
+#define PWR_BASE_PWRACTIVE PWR_CTRL_REG(0x398)
+#define PWR_STACK_PRESENT PWR_CTRL_REG(0x3c0)
+#define PWR_STACK_READY PWR_CTRL_REG(0x3c8)
+#define PWR_STACK_PWRTRANS PWR_CTRL_REG(0x3d0)
+
+#endif /* __PANTHOR_PWR_REGS_H__ */
diff --git a/drivers/gpu/drm/panthor/panthor_regs.h b/drivers/gpu/drm/panthor/panthor_regs.h
deleted file mode 100644
index 08bf06c452d6..000000000000
--- a/drivers/gpu/drm/panthor/panthor_regs.h
+++ /dev/null
@@ -1,291 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 or MIT */
-/* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
-/* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
-/* Copyright 2023 Collabora ltd. */
-/*
- * Register definitions based on mali_kbase_gpu_regmap.h and
- * mali_kbase_gpu_regmap_csf.h
- * (C) COPYRIGHT 2010-2022 ARM Limited. All rights reserved.
- */
-#ifndef __PANTHOR_REGS_H__
-#define __PANTHOR_REGS_H__
-
-#define GPU_ID 0x0
-#define GPU_ARCH_MAJOR(x) ((x) >> 28)
-#define GPU_ARCH_MINOR(x) (((x) & GENMASK(27, 24)) >> 24)
-#define GPU_ARCH_REV(x) (((x) & GENMASK(23, 20)) >> 20)
-#define GPU_PROD_MAJOR(x) (((x) & GENMASK(19, 16)) >> 16)
-#define GPU_VER_MAJOR(x) (((x) & GENMASK(15, 12)) >> 12)
-#define GPU_VER_MINOR(x) (((x) & GENMASK(11, 4)) >> 4)
-#define GPU_VER_STATUS(x) ((x) & GENMASK(3, 0))
-
-#define GPU_L2_FEATURES 0x4
-#define GPU_L2_FEATURES_LINE_SIZE(x) (1 << ((x) & GENMASK(7, 0)))
-
-#define GPU_CORE_FEATURES 0x8
-
-#define GPU_TILER_FEATURES 0xC
-#define GPU_MEM_FEATURES 0x10
-#define GROUPS_L2_COHERENT BIT(0)
-
-#define GPU_MMU_FEATURES 0x14
-#define GPU_MMU_FEATURES_VA_BITS(x) ((x) & GENMASK(7, 0))
-#define GPU_MMU_FEATURES_PA_BITS(x) (((x) >> 8) & GENMASK(7, 0))
-#define GPU_AS_PRESENT 0x18
-#define GPU_CSF_ID 0x1C
-
-#define GPU_INT_RAWSTAT 0x20
-#define GPU_INT_CLEAR 0x24
-#define GPU_INT_MASK 0x28
-#define GPU_INT_STAT 0x2c
-#define GPU_IRQ_FAULT BIT(0)
-#define GPU_IRQ_PROTM_FAULT BIT(1)
-#define GPU_IRQ_RESET_COMPLETED BIT(8)
-#define GPU_IRQ_POWER_CHANGED BIT(9)
-#define GPU_IRQ_POWER_CHANGED_ALL BIT(10)
-#define GPU_IRQ_CLEAN_CACHES_COMPLETED BIT(17)
-#define GPU_IRQ_DOORBELL_MIRROR BIT(18)
-#define GPU_IRQ_MCU_STATUS_CHANGED BIT(19)
-#define GPU_CMD 0x30
-#define GPU_CMD_DEF(type, payload) ((type) | ((payload) << 8))
-#define GPU_SOFT_RESET GPU_CMD_DEF(1, 1)
-#define GPU_HARD_RESET GPU_CMD_DEF(1, 2)
-#define CACHE_CLEAN BIT(0)
-#define CACHE_INV BIT(1)
-#define GPU_FLUSH_CACHES(l2, lsc, oth) \
- GPU_CMD_DEF(4, ((l2) << 0) | ((lsc) << 4) | ((oth) << 8))
-
-#define GPU_STATUS 0x34
-#define GPU_STATUS_ACTIVE BIT(0)
-#define GPU_STATUS_PWR_ACTIVE BIT(1)
-#define GPU_STATUS_PAGE_FAULT BIT(4)
-#define GPU_STATUS_PROTM_ACTIVE BIT(7)
-#define GPU_STATUS_DBG_ENABLED BIT(8)
-
-#define GPU_FAULT_STATUS 0x3C
-#define GPU_FAULT_ADDR 0x40
-#define GPU_L2_CONFIG 0x48
-#define GPU_L2_CONFIG_ASN_HASH_ENABLE BIT(24)
-
-#define GPU_PWR_KEY 0x50
-#define GPU_PWR_KEY_UNLOCK 0x2968A819
-#define GPU_PWR_OVERRIDE0 0x54
-#define GPU_PWR_OVERRIDE1 0x58
-
-#define GPU_FEATURES 0x60
-#define GPU_FEATURES_RAY_INTERSECTION BIT(2)
-#define GPU_FEATURES_RAY_TRAVERSAL BIT(5)
-
-#define GPU_TIMESTAMP_OFFSET 0x88
-#define GPU_CYCLE_COUNT 0x90
-#define GPU_TIMESTAMP 0x98
-
-#define GPU_THREAD_MAX_THREADS 0xA0
-#define GPU_THREAD_MAX_WORKGROUP_SIZE 0xA4
-#define GPU_THREAD_MAX_BARRIER_SIZE 0xA8
-#define GPU_THREAD_FEATURES 0xAC
-
-#define GPU_TEXTURE_FEATURES(n) (0xB0 + ((n) * 4))
-
-#define GPU_SHADER_PRESENT 0x100
-#define GPU_TILER_PRESENT 0x110
-#define GPU_L2_PRESENT 0x120
-
-#define SHADER_READY 0x140
-#define TILER_READY 0x150
-#define L2_READY 0x160
-
-#define SHADER_PWRON 0x180
-#define TILER_PWRON 0x190
-#define L2_PWRON 0x1A0
-
-#define SHADER_PWROFF 0x1C0
-#define TILER_PWROFF 0x1D0
-#define L2_PWROFF 0x1E0
-
-#define SHADER_PWRTRANS 0x200
-#define TILER_PWRTRANS 0x210
-#define L2_PWRTRANS 0x220
-
-#define SHADER_PWRACTIVE 0x240
-#define TILER_PWRACTIVE 0x250
-#define L2_PWRACTIVE 0x260
-
-#define GPU_REVID 0x280
-
-#define GPU_ASN_HASH(n) (0x2C0 + ((n) * 4))
-
-#define GPU_COHERENCY_FEATURES 0x300
-#define GPU_COHERENCY_PROT_BIT(name) BIT(GPU_COHERENCY_ ## name)
-
-#define GPU_COHERENCY_PROTOCOL 0x304
-#define GPU_COHERENCY_ACE_LITE 0
-#define GPU_COHERENCY_ACE 1
-#define GPU_COHERENCY_NONE 31
-
-#define MCU_CONTROL 0x700
-#define MCU_CONTROL_ENABLE 1
-#define MCU_CONTROL_AUTO 2
-#define MCU_CONTROL_DISABLE 0
-
-#define MCU_STATUS 0x704
-#define MCU_STATUS_DISABLED 0
-#define MCU_STATUS_ENABLED 1
-#define MCU_STATUS_HALT 2
-#define MCU_STATUS_FATAL 3
-
-/* Job Control regs */
-#define JOB_INT_RAWSTAT 0x1000
-#define JOB_INT_CLEAR 0x1004
-#define JOB_INT_MASK 0x1008
-#define JOB_INT_STAT 0x100c
-#define JOB_INT_GLOBAL_IF BIT(31)
-#define JOB_INT_CSG_IF(x) BIT(x)
-
-/* MMU regs */
-#define MMU_INT_RAWSTAT 0x2000
-#define MMU_INT_CLEAR 0x2004
-#define MMU_INT_MASK 0x2008
-#define MMU_INT_STAT 0x200c
-
-/* AS_COMMAND register commands */
-
-#define MMU_BASE 0x2400
-#define MMU_AS_SHIFT 6
-#define MMU_AS(as) (MMU_BASE + ((as) << MMU_AS_SHIFT))
-
-#define AS_TRANSTAB(as) (MMU_AS(as) + 0x0)
-#define AS_MEMATTR(as) (MMU_AS(as) + 0x8)
-#define AS_MEMATTR_AARCH64_INNER_ALLOC_IMPL (2 << 2)
-#define AS_MEMATTR_AARCH64_INNER_ALLOC_EXPL(w, r) ((3 << 2) | \
- ((w) ? BIT(0) : 0) | \
- ((r) ? BIT(1) : 0))
-#define AS_MEMATTR_AARCH64_SH_MIDGARD_INNER (0 << 4)
-#define AS_MEMATTR_AARCH64_SH_CPU_INNER (1 << 4)
-#define AS_MEMATTR_AARCH64_SH_CPU_INNER_SHADER_COH (2 << 4)
-#define AS_MEMATTR_AARCH64_SHARED (0 << 6)
-#define AS_MEMATTR_AARCH64_INNER_OUTER_NC (1 << 6)
-#define AS_MEMATTR_AARCH64_INNER_OUTER_WB (2 << 6)
-#define AS_MEMATTR_AARCH64_FAULT (3 << 6)
-#define AS_LOCKADDR(as) (MMU_AS(as) + 0x10)
-#define AS_COMMAND(as) (MMU_AS(as) + 0x18)
-#define AS_COMMAND_NOP 0
-#define AS_COMMAND_UPDATE 1
-#define AS_COMMAND_LOCK 2
-#define AS_COMMAND_UNLOCK 3
-#define AS_COMMAND_FLUSH_PT 4
-#define AS_COMMAND_FLUSH_MEM 5
-#define AS_LOCK_REGION_MIN_SIZE (1ULL << 15)
-#define AS_FAULTSTATUS(as) (MMU_AS(as) + 0x1C)
-#define AS_FAULTSTATUS_ACCESS_TYPE_MASK (0x3 << 8)
-#define AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC (0x0 << 8)
-#define AS_FAULTSTATUS_ACCESS_TYPE_EX (0x1 << 8)
-#define AS_FAULTSTATUS_ACCESS_TYPE_READ (0x2 << 8)
-#define AS_FAULTSTATUS_ACCESS_TYPE_WRITE (0x3 << 8)
-#define AS_FAULTADDRESS(as) (MMU_AS(as) + 0x20)
-#define AS_STATUS(as) (MMU_AS(as) + 0x28)
-#define AS_STATUS_AS_ACTIVE BIT(0)
-#define AS_TRANSCFG(as) (MMU_AS(as) + 0x30)
-#define AS_TRANSCFG_ADRMODE_UNMAPPED (1 << 0)
-#define AS_TRANSCFG_ADRMODE_IDENTITY (2 << 0)
-#define AS_TRANSCFG_ADRMODE_AARCH64_4K (6 << 0)
-#define AS_TRANSCFG_ADRMODE_AARCH64_64K (8 << 0)
-#define AS_TRANSCFG_INA_BITS(x) ((x) << 6)
-#define AS_TRANSCFG_OUTA_BITS(x) ((x) << 14)
-#define AS_TRANSCFG_SL_CONCAT BIT(22)
-#define AS_TRANSCFG_PTW_MEMATTR_NC (1 << 24)
-#define AS_TRANSCFG_PTW_MEMATTR_WB (2 << 24)
-#define AS_TRANSCFG_PTW_SH_NS (0 << 28)
-#define AS_TRANSCFG_PTW_SH_OS (2 << 28)
-#define AS_TRANSCFG_PTW_SH_IS (3 << 28)
-#define AS_TRANSCFG_PTW_RA BIT(30)
-#define AS_TRANSCFG_DISABLE_HIER_AP BIT(33)
-#define AS_TRANSCFG_DISABLE_AF_FAULT BIT(34)
-#define AS_TRANSCFG_WXN BIT(35)
-#define AS_TRANSCFG_XREADABLE BIT(36)
-#define AS_FAULTEXTRA(as) (MMU_AS(as) + 0x38)
-
-#define CSF_GPU_LATEST_FLUSH_ID 0x10000
-
-#define CSF_DOORBELL(i) (0x80000 + ((i) * 0x10000))
-#define CSF_GLB_DOORBELL_ID 0
-
-/* PWR Control registers */
-
-#define PWR_CONTROL_BASE 0x800
-#define PWR_CTRL_REG(x) (PWR_CONTROL_BASE + (x))
-
-#define PWR_INT_RAWSTAT PWR_CTRL_REG(0x0)
-#define PWR_INT_CLEAR PWR_CTRL_REG(0x4)
-#define PWR_INT_MASK PWR_CTRL_REG(0x8)
-#define PWR_INT_STAT PWR_CTRL_REG(0xc)
-#define PWR_IRQ_POWER_CHANGED_SINGLE BIT(0)
-#define PWR_IRQ_POWER_CHANGED_ALL BIT(1)
-#define PWR_IRQ_DELEGATION_CHANGED BIT(2)
-#define PWR_IRQ_RESET_COMPLETED BIT(3)
-#define PWR_IRQ_RETRACT_COMPLETED BIT(4)
-#define PWR_IRQ_INSPECT_COMPLETED BIT(5)
-#define PWR_IRQ_COMMAND_NOT_ALLOWED BIT(30)
-#define PWR_IRQ_COMMAND_INVALID BIT(31)
-
-#define PWR_STATUS PWR_CTRL_REG(0x20)
-#define PWR_STATUS_ALLOW_L2 BIT_U64(0)
-#define PWR_STATUS_ALLOW_TILER BIT_U64(1)
-#define PWR_STATUS_ALLOW_SHADER BIT_U64(8)
-#define PWR_STATUS_ALLOW_BASE BIT_U64(14)
-#define PWR_STATUS_ALLOW_STACK BIT_U64(15)
-#define PWR_STATUS_DOMAIN_ALLOWED(x) BIT_U64(x)
-#define PWR_STATUS_DELEGATED_L2 BIT_U64(16)
-#define PWR_STATUS_DELEGATED_TILER BIT_U64(17)
-#define PWR_STATUS_DELEGATED_SHADER BIT_U64(24)
-#define PWR_STATUS_DELEGATED_BASE BIT_U64(30)
-#define PWR_STATUS_DELEGATED_STACK BIT_U64(31)
-#define PWR_STATUS_DELEGATED_SHIFT 16
-#define PWR_STATUS_DOMAIN_DELEGATED(x) BIT_U64((x) + PWR_STATUS_DELEGATED_SHIFT)
-#define PWR_STATUS_ALLOW_SOFT_RESET BIT_U64(33)
-#define PWR_STATUS_ALLOW_FAST_RESET BIT_U64(34)
-#define PWR_STATUS_POWER_PENDING BIT_U64(41)
-#define PWR_STATUS_RESET_PENDING BIT_U64(42)
-#define PWR_STATUS_RETRACT_PENDING BIT_U64(43)
-#define PWR_STATUS_INSPECT_PENDING BIT_U64(44)
-
-#define PWR_COMMAND PWR_CTRL_REG(0x28)
-#define PWR_COMMAND_POWER_UP 0x10
-#define PWR_COMMAND_POWER_DOWN 0x11
-#define PWR_COMMAND_DELEGATE 0x20
-#define PWR_COMMAND_RETRACT 0x21
-#define PWR_COMMAND_RESET_SOFT 0x31
-#define PWR_COMMAND_RESET_FAST 0x32
-#define PWR_COMMAND_INSPECT 0xF0
-#define PWR_COMMAND_DOMAIN_L2 0
-#define PWR_COMMAND_DOMAIN_TILER 1
-#define PWR_COMMAND_DOMAIN_SHADER 8
-#define PWR_COMMAND_DOMAIN_BASE 14
-#define PWR_COMMAND_DOMAIN_STACK 15
-#define PWR_COMMAND_SUBDOMAIN_RTU BIT(0)
-#define PWR_COMMAND_DEF(cmd, domain, subdomain) \
- (((subdomain) << 16) | ((domain) << 8) | (cmd))
-
-#define PWR_CMDARG PWR_CTRL_REG(0x30)
-
-#define PWR_L2_PRESENT PWR_CTRL_REG(0x100)
-#define PWR_L2_READY PWR_CTRL_REG(0x108)
-#define PWR_L2_PWRTRANS PWR_CTRL_REG(0x110)
-#define PWR_L2_PWRACTIVE PWR_CTRL_REG(0x118)
-#define PWR_TILER_PRESENT PWR_CTRL_REG(0x140)
-#define PWR_TILER_READY PWR_CTRL_REG(0x148)
-#define PWR_TILER_PWRTRANS PWR_CTRL_REG(0x150)
-#define PWR_TILER_PWRACTIVE PWR_CTRL_REG(0x158)
-#define PWR_SHADER_PRESENT PWR_CTRL_REG(0x200)
-#define PWR_SHADER_READY PWR_CTRL_REG(0x208)
-#define PWR_SHADER_PWRTRANS PWR_CTRL_REG(0x210)
-#define PWR_SHADER_PWRACTIVE PWR_CTRL_REG(0x218)
-#define PWR_BASE_PRESENT PWR_CTRL_REG(0x380)
-#define PWR_BASE_READY PWR_CTRL_REG(0x388)
-#define PWR_BASE_PWRTRANS PWR_CTRL_REG(0x390)
-#define PWR_BASE_PWRACTIVE PWR_CTRL_REG(0x398)
-#define PWR_STACK_PRESENT PWR_CTRL_REG(0x3c0)
-#define PWR_STACK_READY PWR_CTRL_REG(0x3c8)
-#define PWR_STACK_PWRTRANS PWR_CTRL_REG(0x3d0)
-
-#endif
diff --git a/drivers/gpu/drm/panthor/panthor_sched.c b/drivers/gpu/drm/panthor/panthor_sched.c
index 7c8d350da02f..70b8a22b3ed7 100644
--- a/drivers/gpu/drm/panthor/panthor_sched.c
+++ b/drivers/gpu/drm/panthor/panthor_sched.c
@@ -28,11 +28,12 @@
#include "panthor_devfreq.h"
#include "panthor_device.h"
#include "panthor_fw.h"
+#include "panthor_fw_regs.h"
#include "panthor_gem.h"
#include "panthor_gpu.h"
+#include "panthor_gpu_regs.h"
#include "panthor_heap.h"
#include "panthor_mmu.h"
-#include "panthor_regs.h"
#include "panthor_sched.h"
/**
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 2/8] drm/panthor: Split register definitions by components
2026-04-10 16:46 ` [PATCH 2/8] drm/panthor: Split register definitions by components Karunika Choo
@ 2026-04-10 18:08 ` Boris Brezillon
0 siblings, 0 replies; 17+ messages in thread
From: Boris Brezillon @ 2026-04-10 18:08 UTC (permalink / raw)
To: Karunika Choo
Cc: dri-devel, nd, Steven Price, Liviu Dudau, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
linux-kernel
On Fri, 10 Apr 2026 17:46:31 +0100
Karunika Choo <karunika.choo@arm.com> wrote:
> --- /dev/null
> +++ b/drivers/gpu/drm/panthor/panthor_hw_regs.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: GPL-2.0 or MIT */
> +/* Copyright 2026 ARM Limited. All rights reserved. */
> +
> +#ifndef __PANTHOR_HW_REGS_H__
> +#define __PANTHOR_HW_REGS_H__
> +
> +#define GPU_ID 0x0
> +#define GPU_ARCH_MAJOR(x) ((x) >> 28)
> +#define GPU_ARCH_MINOR(x) (((x) & GENMASK(27, 24)) >> 24)
> +#define GPU_ARCH_REV(x) (((x) & GENMASK(23, 20)) >> 20)
> +#define GPU_PROD_MAJOR(x) (((x) & GENMASK(19, 16)) >> 16)
> +#define GPU_VER_MAJOR(x) (((x) & GENMASK(15, 12)) >> 12)
> +#define GPU_VER_MINOR(x) (((x) & GENMASK(11, 4)) >> 4)
> +#define GPU_VER_STATUS(x) ((x) & GENMASK(3, 0))
Any particular reason for not having those defined in
panthor_gpu_regs.h?
> +
> +#endif /* __PANTHOR_HW_REGS_H__ */
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/8] drm/panthor: Replace cross-component register accesses with helpers
2026-04-10 16:46 [PATCH 0/8] drm/panthor: Localize register access by component Karunika Choo
2026-04-10 16:46 ` [PATCH 1/8] drm/panthor: Pass an iomem pointer to GPU register access helpers Karunika Choo
2026-04-10 16:46 ` [PATCH 2/8] drm/panthor: Split register definitions by components Karunika Choo
@ 2026-04-10 16:46 ` Karunika Choo
2026-04-10 17:55 ` Boris Brezillon
2026-04-10 16:46 ` [PATCH 4/8] drm/panthor: Store IRQ register base iomem pointer in panthor_irq Karunika Choo
` (4 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Karunika Choo @ 2026-04-10 16:46 UTC (permalink / raw)
To: dri-devel
Cc: nd, Boris Brezillon, Steven Price, Liviu Dudau, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
linux-kernel
Stop reaching into other components' registers directly and route those
operations through the component that owns them.
Move the timestamp/coherency helpers into panthor_gpu, add a doorbell
helper, and update call sites accordingly. This keeps register knowledge
local to each block and avoids spreading cross-component register
accesses across the driver.
This is a preparatory cleanup for using per-component iomem bases.
Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
drivers/gpu/drm/panthor/panthor_device.c | 27 ----------------
drivers/gpu/drm/panthor/panthor_drv.c | 7 ++---
drivers/gpu/drm/panthor/panthor_fw.c | 15 ++++++---
drivers/gpu/drm/panthor/panthor_fw.h | 1 +
drivers/gpu/drm/panthor/panthor_gpu.c | 40 ++++++++++++++++++++++++
drivers/gpu/drm/panthor/panthor_gpu.h | 6 ++++
drivers/gpu/drm/panthor/panthor_pwr.c | 2 +-
drivers/gpu/drm/panthor/panthor_sched.c | 2 +-
8 files changed, 62 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/panthor/panthor_device.c
index f876b13492ae..bd417d6ae8c0 100644
--- a/drivers/gpu/drm/panthor/panthor_device.c
+++ b/drivers/gpu/drm/panthor/panthor_device.c
@@ -22,38 +22,11 @@
#include "panthor_fw_regs.h"
#include "panthor_gem.h"
#include "panthor_gpu.h"
-#include "panthor_gpu_regs.h"
#include "panthor_hw.h"
#include "panthor_mmu.h"
#include "panthor_pwr.h"
#include "panthor_sched.h"
-static int panthor_gpu_coherency_init(struct panthor_device *ptdev)
-{
- BUILD_BUG_ON(GPU_COHERENCY_NONE != DRM_PANTHOR_GPU_COHERENCY_NONE);
- BUILD_BUG_ON(GPU_COHERENCY_ACE_LITE != DRM_PANTHOR_GPU_COHERENCY_ACE_LITE);
- BUILD_BUG_ON(GPU_COHERENCY_ACE != DRM_PANTHOR_GPU_COHERENCY_ACE);
-
- /* Start with no coherency, and update it if the device is flagged coherent. */
- ptdev->gpu_info.selected_coherency = GPU_COHERENCY_NONE;
- ptdev->coherent = device_get_dma_attr(ptdev->base.dev) == DEV_DMA_COHERENT;
-
- if (!ptdev->coherent)
- return 0;
-
- /* Check if the ACE-Lite coherency protocol is actually supported by the GPU.
- * ACE protocol has never been supported for command stream frontend GPUs.
- */
- if ((gpu_read(ptdev->iomem, GPU_COHERENCY_FEATURES) &
- GPU_COHERENCY_PROT_BIT(ACE_LITE))) {
- ptdev->gpu_info.selected_coherency = GPU_COHERENCY_ACE_LITE;
- return 0;
- }
-
- drm_err(&ptdev->base, "Coherency not supported by the device");
- return -ENOTSUPP;
-}
-
static int panthor_clk_init(struct panthor_device *ptdev)
{
ptdev->clks.core = devm_clk_get(ptdev->base.dev, NULL);
diff --git a/drivers/gpu/drm/panthor/panthor_drv.c b/drivers/gpu/drm/panthor/panthor_drv.c
index e63210b01e6e..8cd39e6c3f5c 100644
--- a/drivers/gpu/drm/panthor/panthor_drv.c
+++ b/drivers/gpu/drm/panthor/panthor_drv.c
@@ -34,7 +34,6 @@
#include "panthor_fw.h"
#include "panthor_gem.h"
#include "panthor_gpu.h"
-#include "panthor_gpu_regs.h"
#include "panthor_heap.h"
#include "panthor_mmu.h"
#include "panthor_sched.h"
@@ -839,7 +838,7 @@ static int panthor_query_timestamp_info(struct panthor_device *ptdev,
}
if (flags & DRM_PANTHOR_TIMESTAMP_GPU_OFFSET)
- arg->timestamp_offset = gpu_read64(ptdev->iomem, GPU_TIMESTAMP_OFFSET);
+ arg->timestamp_offset = panthor_gpu_get_timestap_offset(ptdev);
else
arg->timestamp_offset = 0;
@@ -854,7 +853,7 @@ static int panthor_query_timestamp_info(struct panthor_device *ptdev,
query_start_time = 0;
if (flags & DRM_PANTHOR_TIMESTAMP_GPU)
- arg->current_timestamp = gpu_read64_counter(ptdev->iomem, GPU_TIMESTAMP);
+ arg->current_timestamp = panthor_gpu_get_timestap(ptdev);
else
arg->current_timestamp = 0;
@@ -870,7 +869,7 @@ static int panthor_query_timestamp_info(struct panthor_device *ptdev,
}
if (flags & DRM_PANTHOR_TIMESTAMP_GPU_CYCLE_COUNT)
- arg->cycle_count = gpu_read64_counter(ptdev->iomem, GPU_CYCLE_COUNT);
+ arg->cycle_count = panthor_gpu_get_cycle_count(ptdev);
else
arg->cycle_count = 0;
diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor/panthor_fw.c
index 4704275b9c8f..1c13a4884201 100644
--- a/drivers/gpu/drm/panthor/panthor_fw.c
+++ b/drivers/gpu/drm/panthor/panthor_fw.c
@@ -1054,7 +1054,7 @@ static void panthor_fw_init_global_iface(struct panthor_device *ptdev)
GLB_CFG_POWEROFF_TIMER |
GLB_CFG_PROGRESS_TIMER);
- gpu_write(ptdev->iomem, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
+ panthor_fw_ring_doorbell(ptdev, CSF_GLB_DOORBELL_ID);
/* Kick the watchdog. */
mod_delayed_work(ptdev->reset.wq, &ptdev->fw->watchdog.ping_work,
@@ -1156,7 +1156,7 @@ static void panthor_fw_halt_mcu(struct panthor_device *ptdev)
else
panthor_fw_update_reqs(glb_iface, req, GLB_HALT, GLB_HALT);
- gpu_write(ptdev->iomem, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
+ panthor_fw_ring_doorbell(ptdev, CSF_GLB_DOORBELL_ID);
}
static bool panthor_fw_wait_mcu_halted(struct panthor_device *ptdev)
@@ -1400,6 +1400,11 @@ int panthor_fw_csg_wait_acks(struct panthor_device *ptdev, u32 csg_slot,
return ret;
}
+void panthor_fw_ring_doorbell(struct panthor_device *ptdev, u32 doorbell_id)
+{
+ gpu_write(ptdev->iomem, CSF_DOORBELL(doorbell_id), 1);
+}
+
/**
* panthor_fw_ring_csg_doorbells() - Ring command stream group doorbells.
* @ptdev: Device.
@@ -1413,8 +1418,8 @@ void panthor_fw_ring_csg_doorbells(struct panthor_device *ptdev, u32 csg_mask)
{
struct panthor_fw_global_iface *glb_iface = panthor_fw_get_glb_iface(ptdev);
- panthor_fw_toggle_reqs(glb_iface, doorbell_req, doorbell_ack, csg_mask);
- gpu_write(ptdev->iomem, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
+ panthor_fw_toggle_reqs(glb_iface, doorbell_req, doorbell_ack, csg_mask);\
+ panthor_fw_ring_doorbell(ptdev, CSF_GLB_DOORBELL_ID);
}
static void panthor_fw_ping_work(struct work_struct *work)
@@ -1429,7 +1434,7 @@ static void panthor_fw_ping_work(struct work_struct *work)
return;
panthor_fw_toggle_reqs(glb_iface, req, ack, GLB_PING);
- gpu_write(ptdev->iomem, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);
+ panthor_fw_ring_doorbell(ptdev, CSF_GLB_DOORBELL_ID);
ret = panthor_fw_glb_wait_acks(ptdev, GLB_PING, &acked, 100);
if (ret) {
diff --git a/drivers/gpu/drm/panthor/panthor_fw.h b/drivers/gpu/drm/panthor/panthor_fw.h
index fbdc21469ba3..a99a9b6f4825 100644
--- a/drivers/gpu/drm/panthor/panthor_fw.h
+++ b/drivers/gpu/drm/panthor/panthor_fw.h
@@ -500,6 +500,7 @@ int panthor_fw_csg_wait_acks(struct panthor_device *ptdev, u32 csg_id, u32 req_m
int panthor_fw_glb_wait_acks(struct panthor_device *ptdev, u32 req_mask, u32 *acked,
u32 timeout_ms);
+void panthor_fw_ring_doorbell(struct panthor_device *ptdev, u32 doorbell_id);
void panthor_fw_ring_csg_doorbells(struct panthor_device *ptdev, u32 csg_slot);
struct panthor_kernel_bo *
diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c
index fecc30747acf..ef0aca2b7532 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu.c
+++ b/drivers/gpu/drm/panthor/panthor_gpu.c
@@ -427,3 +427,43 @@ void panthor_gpu_resume(struct panthor_device *ptdev)
panthor_hw_l2_power_on(ptdev);
}
+u64 panthor_gpu_get_timestap(struct panthor_device *ptdev)
+{
+ return gpu_read64_counter(ptdev->iomem, GPU_TIMESTAMP);
+}
+
+u64 panthor_gpu_get_timestap_offset(struct panthor_device *ptdev)
+{
+ return gpu_read64(ptdev->iomem, GPU_TIMESTAMP_OFFSET);
+}
+
+u64 panthor_gpu_get_cycle_count(struct panthor_device *ptdev)
+{
+ return gpu_read64_counter(ptdev->iomem, GPU_CYCLE_COUNT);
+}
+
+int panthor_gpu_coherency_init(struct panthor_device *ptdev)
+{
+ BUILD_BUG_ON(GPU_COHERENCY_NONE != DRM_PANTHOR_GPU_COHERENCY_NONE);
+ BUILD_BUG_ON(GPU_COHERENCY_ACE_LITE != DRM_PANTHOR_GPU_COHERENCY_ACE_LITE);
+ BUILD_BUG_ON(GPU_COHERENCY_ACE != DRM_PANTHOR_GPU_COHERENCY_ACE);
+
+ /* Start with no coherency, and update it if the device is flagged coherent. */
+ ptdev->gpu_info.selected_coherency = GPU_COHERENCY_NONE;
+ ptdev->coherent = device_get_dma_attr(ptdev->base.dev) == DEV_DMA_COHERENT;
+
+ if (!ptdev->coherent)
+ return 0;
+
+ /* Check if the ACE-Lite coherency protocol is actually supported by the GPU.
+ * ACE protocol has never been supported for command stream frontend GPUs.
+ */
+ if ((gpu_read(ptdev->iomem, GPU_COHERENCY_FEATURES) &
+ GPU_COHERENCY_PROT_BIT(ACE_LITE))) {
+ ptdev->gpu_info.selected_coherency = GPU_COHERENCY_ACE_LITE;
+ return 0;
+ }
+
+ drm_err(&ptdev->base, "Coherency not supported by the device");
+ return -ENOTSUPP;
+}
diff --git a/drivers/gpu/drm/panthor/panthor_gpu.h b/drivers/gpu/drm/panthor/panthor_gpu.h
index 12c263a39928..c22378e5ce48 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu.h
+++ b/drivers/gpu/drm/panthor/panthor_gpu.h
@@ -54,4 +54,10 @@ int panthor_gpu_soft_reset(struct panthor_device *ptdev);
void panthor_gpu_power_changed_off(struct panthor_device *ptdev);
int panthor_gpu_power_changed_on(struct panthor_device *ptdev);
+u64 panthor_gpu_get_timestap(struct panthor_device *ptdev);
+u64 panthor_gpu_get_timestap_offset(struct panthor_device *ptdev);
+u64 panthor_gpu_get_cycle_count(struct panthor_device *ptdev);
+
+int panthor_gpu_coherency_init(struct panthor_device *ptdev);
+
#endif
diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/panthor/panthor_pwr.c
index 306592ff2227..aafb0c5c7d23 100644
--- a/drivers/gpu/drm/panthor/panthor_pwr.c
+++ b/drivers/gpu/drm/panthor/panthor_pwr.c
@@ -199,7 +199,7 @@ static int panthor_pwr_domain_wait_transition(struct panthor_device *ptdev, u32
static void panthor_pwr_debug_info_show(struct panthor_device *ptdev)
{
- drm_info(&ptdev->base, "GPU_FEATURES: 0x%016llx", gpu_read64(ptdev->iomem, GPU_FEATURES));
+ drm_info(&ptdev->base, "GPU_FEATURES: 0x%016llx", ptdev->gpu_info.gpu_features);
drm_info(&ptdev->base, "PWR_STATUS: 0x%016llx", gpu_read64(ptdev->iomem, PWR_STATUS));
drm_info(&ptdev->base, "L2_PRESENT: 0x%016llx", gpu_read64(ptdev->iomem, PWR_L2_PRESENT));
drm_info(&ptdev->base, "L2_PWRTRANS: 0x%016llx", gpu_read64(ptdev->iomem, PWR_L2_PWRTRANS));
diff --git a/drivers/gpu/drm/panthor/panthor_sched.c b/drivers/gpu/drm/panthor/panthor_sched.c
index 70b8a22b3ed7..60e7b4e20a13 100644
--- a/drivers/gpu/drm/panthor/panthor_sched.c
+++ b/drivers/gpu/drm/panthor/panthor_sched.c
@@ -3373,7 +3373,7 @@ queue_run_job(struct drm_sched_job *sched_job)
if (resume_tick)
sched_resume_tick(ptdev);
- gpu_write(ptdev->iomem, CSF_DOORBELL(queue->doorbell_id), 1);
+ panthor_fw_ring_doorbell(ptdev, queue->doorbell_id);
if (!sched->pm.has_ref &&
!(group->blocked_queues & BIT(job->queue_idx))) {
pm_runtime_get(ptdev->base.dev);
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 3/8] drm/panthor: Replace cross-component register accesses with helpers
2026-04-10 16:46 ` [PATCH 3/8] drm/panthor: Replace cross-component register accesses with helpers Karunika Choo
@ 2026-04-10 17:55 ` Boris Brezillon
0 siblings, 0 replies; 17+ messages in thread
From: Boris Brezillon @ 2026-04-10 17:55 UTC (permalink / raw)
To: Karunika Choo
Cc: dri-devel, nd, Steven Price, Liviu Dudau, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
linux-kernel
On Fri, 10 Apr 2026 17:46:32 +0100
Karunika Choo <karunika.choo@arm.com> wrote:
> +u64 panthor_gpu_get_timestap(struct panthor_device *ptdev)
> +{
> + return gpu_read64_counter(ptdev->iomem, GPU_TIMESTAMP);
> +}
> +
> +u64 panthor_gpu_get_timestap_offset(struct panthor_device *ptdev)
> +{
> + return gpu_read64(ptdev->iomem, GPU_TIMESTAMP_OFFSET);
> +}
There's a typo here: s/timestap/timestamp/
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 4/8] drm/panthor: Store IRQ register base iomem pointer in panthor_irq
2026-04-10 16:46 [PATCH 0/8] drm/panthor: Localize register access by component Karunika Choo
` (2 preceding siblings ...)
2026-04-10 16:46 ` [PATCH 3/8] drm/panthor: Replace cross-component register accesses with helpers Karunika Choo
@ 2026-04-10 16:46 ` Karunika Choo
2026-04-10 17:53 ` Boris Brezillon
2026-04-10 16:46 ` [PATCH 5/8] drm/panthor: Use a local iomem base for GPU registers Karunika Choo
` (3 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Karunika Choo @ 2026-04-10 16:46 UTC (permalink / raw)
To: dri-devel
Cc: nd, Boris Brezillon, Steven Price, Liviu Dudau, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
linux-kernel
Update common IRQ handling code to work from an IRQ-local iomem base
instead of referencing block-specific interrupt register offsets.
Store the interrupt base address iomem pointer in struct panthor_irq and
switch the shared IRQ helpers to use generic INT_* offsets from that
local base. This removes the need for each caller to expose absolute IRQ
register addresses while keeping the common IRQ flow unchanged.
No functional change intended.
Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
drivers/gpu/drm/panthor/panthor_device.h | 32 ++++++++++++++--------
drivers/gpu/drm/panthor/panthor_fw.c | 4 +--
drivers/gpu/drm/panthor/panthor_fw_regs.h | 2 ++
drivers/gpu/drm/panthor/panthor_gpu.c | 5 ++--
drivers/gpu/drm/panthor/panthor_gpu_regs.h | 1 +
drivers/gpu/drm/panthor/panthor_mmu.c | 5 ++--
drivers/gpu/drm/panthor/panthor_mmu_regs.h | 3 ++
drivers/gpu/drm/panthor/panthor_pwr.c | 6 ++--
8 files changed, 38 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/panthor/panthor_device.h
index 285bf7e4439e..35a70df4a5da 100644
--- a/drivers/gpu/drm/panthor/panthor_device.h
+++ b/drivers/gpu/drm/panthor/panthor_device.h
@@ -82,6 +82,9 @@ struct panthor_irq {
/** @ptdev: Panthor device */
struct panthor_device *ptdev;
+ /** @iomem: CPU mapping of IRQ base address */
+ void __iomem *iomem;
+
/** @irq: IRQ number. */
int irq;
@@ -488,6 +491,11 @@ panthor_exception_is_fault(u32 exception_code)
const char *panthor_exception_name(struct panthor_device *ptdev,
u32 exception_code);
+#define INT_RAWSTAT 0x0
+#define INT_CLEAR 0x4
+#define INT_MASK 0x8
+#define INT_STAT 0xc
+
/**
* PANTHOR_IRQ_HANDLER() - Define interrupt handlers and the interrupt
* registration function.
@@ -498,14 +506,13 @@ const char *panthor_exception_name(struct panthor_device *ptdev,
*
* void (*handler)(struct panthor_device *, u32 status);
*/
-#define PANTHOR_IRQ_HANDLER(__name, __reg_prefix, __handler) \
+#define PANTHOR_IRQ_HANDLER(__name, __handler) \
static irqreturn_t panthor_ ## __name ## _irq_raw_handler(int irq, void *data) \
{ \
struct panthor_irq *pirq = data; \
- struct panthor_device *ptdev = pirq->ptdev; \
enum panthor_irq_state old_state; \
\
- if (!gpu_read(ptdev->iomem, __reg_prefix ## _INT_STAT)) \
+ if (!gpu_read(pirq->iomem, INT_STAT)) \
return IRQ_NONE; \
\
guard(spinlock_irqsave)(&pirq->mask_lock); \
@@ -515,7 +522,7 @@ static irqreturn_t panthor_ ## __name ## _irq_raw_handler(int irq, void *data)
if (old_state != PANTHOR_IRQ_STATE_ACTIVE) \
return IRQ_NONE; \
\
- gpu_write(ptdev->iomem, __reg_prefix ## _INT_MASK, 0); \
+ gpu_write(pirq->iomem, INT_MASK, 0); \
return IRQ_WAKE_THREAD; \
} \
\
@@ -534,7 +541,7 @@ static irqreturn_t panthor_ ## __name ## _irq_threaded_handler(int irq, void *da
* right before the HW event kicks in. TLDR; it's all expected races we're \
* covered for. \
*/ \
- u32 status = gpu_read(ptdev->iomem, __reg_prefix ## _INT_RAWSTAT) & pirq->mask; \
+ u32 status = gpu_read(pirq->iomem, INT_RAWSTAT) & pirq->mask; \
\
if (!status) \
break; \
@@ -550,7 +557,7 @@ static irqreturn_t panthor_ ## __name ## _irq_threaded_handler(int irq, void *da
PANTHOR_IRQ_STATE_PROCESSING, \
PANTHOR_IRQ_STATE_ACTIVE); \
if (old_state == PANTHOR_IRQ_STATE_PROCESSING) \
- gpu_write(ptdev->iomem, __reg_prefix ## _INT_MASK, pirq->mask); \
+ gpu_write(pirq->iomem, INT_MASK, pirq->mask); \
} \
\
return ret; \
@@ -560,7 +567,7 @@ static inline void panthor_ ## __name ## _irq_suspend(struct panthor_irq *pirq)
{ \
scoped_guard(spinlock_irqsave, &pirq->mask_lock) { \
atomic_set(&pirq->state, PANTHOR_IRQ_STATE_SUSPENDING); \
- gpu_write(pirq->ptdev->iomem, __reg_prefix ## _INT_MASK, 0); \
+ gpu_write(pirq->iomem, INT_MASK, 0); \
} \
synchronize_irq(pirq->irq); \
atomic_set(&pirq->state, PANTHOR_IRQ_STATE_SUSPENDED); \
@@ -571,17 +578,18 @@ static inline void panthor_ ## __name ## _irq_resume(struct panthor_irq *pirq)
guard(spinlock_irqsave)(&pirq->mask_lock); \
\
atomic_set(&pirq->state, PANTHOR_IRQ_STATE_ACTIVE); \
- gpu_write(pirq->ptdev->iomem, __reg_prefix ## _INT_CLEAR, pirq->mask); \
- gpu_write(pirq->ptdev->iomem, __reg_prefix ## _INT_MASK, pirq->mask); \
+ gpu_write(pirq->iomem, INT_CLEAR, pirq->mask); \
+ gpu_write(pirq->iomem, INT_MASK, pirq->mask); \
} \
\
static int panthor_request_ ## __name ## _irq(struct panthor_device *ptdev, \
struct panthor_irq *pirq, \
- int irq, u32 mask) \
+ int irq, u32 mask, u32 irq_baseaddr) \
{ \
pirq->ptdev = ptdev; \
pirq->irq = irq; \
pirq->mask = mask; \
+ pirq->iomem = ptdev->iomem + irq_baseaddr; \
spin_lock_init(&pirq->mask_lock); \
panthor_ ## __name ## _irq_resume(pirq); \
\
@@ -603,7 +611,7 @@ static inline void panthor_ ## __name ## _irq_enable_events(struct panthor_irq *
* If the IRQ is suspended/suspending, the mask is restored at resume time. \
*/ \
if (atomic_read(&pirq->state) == PANTHOR_IRQ_STATE_ACTIVE) \
- gpu_write(pirq->ptdev->iomem, __reg_prefix ## _INT_MASK, pirq->mask); \
+ gpu_write(pirq->iomem, INT_MASK, pirq->mask); \
} \
\
static inline void panthor_ ## __name ## _irq_disable_events(struct panthor_irq *pirq, u32 mask)\
@@ -617,7 +625,7 @@ static inline void panthor_ ## __name ## _irq_disable_events(struct panthor_irq
* If the IRQ is suspended/suspending, the mask is restored at resume time. \
*/ \
if (atomic_read(&pirq->state) == PANTHOR_IRQ_STATE_ACTIVE) \
- gpu_write(pirq->ptdev->iomem, __reg_prefix ## _INT_MASK, pirq->mask); \
+ gpu_write(pirq->iomem, INT_MASK, pirq->mask); \
}
extern struct workqueue_struct *panthor_cleanup_wq;
diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor/panthor_fw.c
index 1c13a4884201..20747f42759f 100644
--- a/drivers/gpu/drm/panthor/panthor_fw.c
+++ b/drivers/gpu/drm/panthor/panthor_fw.c
@@ -1088,7 +1088,7 @@ static void panthor_job_irq_handler(struct panthor_device *ptdev, u32 status)
trace_gpu_job_irq(ptdev->base.dev, status, duration);
}
}
-PANTHOR_IRQ_HANDLER(job, JOB, panthor_job_irq_handler);
+PANTHOR_IRQ_HANDLER(job, panthor_job_irq_handler);
static int panthor_fw_start(struct panthor_device *ptdev)
{
@@ -1470,7 +1470,7 @@ int panthor_fw_init(struct panthor_device *ptdev)
if (irq <= 0)
return -ENODEV;
- ret = panthor_request_job_irq(ptdev, &fw->irq, irq, 0);
+ ret = panthor_request_job_irq(ptdev, &fw->irq, irq, 0, JOB_INT_BASE);
if (ret) {
drm_err(&ptdev->base, "failed to request job irq");
return ret;
diff --git a/drivers/gpu/drm/panthor/panthor_fw_regs.h b/drivers/gpu/drm/panthor/panthor_fw_regs.h
index d523d41e18dd..eeb41aff249b 100644
--- a/drivers/gpu/drm/panthor/panthor_fw_regs.h
+++ b/drivers/gpu/drm/panthor/panthor_fw_regs.h
@@ -15,6 +15,8 @@
#define MCU_STATUS_HALT 2
#define MCU_STATUS_FATAL 3
+#define JOB_INT_BASE 0x1000
+
#define JOB_INT_RAWSTAT 0x1000
#define JOB_INT_CLEAR 0x1004
#define JOB_INT_MASK 0x1008
diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c
index ef0aca2b7532..3ddce35ed8b5 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu.c
+++ b/drivers/gpu/drm/panthor/panthor_gpu.c
@@ -110,7 +110,7 @@ static void panthor_gpu_irq_handler(struct panthor_device *ptdev, u32 status)
}
spin_unlock(&ptdev->gpu->reqs_lock);
}
-PANTHOR_IRQ_HANDLER(gpu, GPU, panthor_gpu_irq_handler);
+PANTHOR_IRQ_HANDLER(gpu, panthor_gpu_irq_handler);
/**
* panthor_gpu_unplug() - Called when the GPU is unplugged.
@@ -162,7 +162,8 @@ int panthor_gpu_init(struct panthor_device *ptdev)
if (irq < 0)
return irq;
- ret = panthor_request_gpu_irq(ptdev, &ptdev->gpu->irq, irq, GPU_INTERRUPTS_MASK);
+ ret = panthor_request_gpu_irq(ptdev, &ptdev->gpu->irq, irq,
+ GPU_INTERRUPTS_MASK, GPU_INT_BASE);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/panthor/panthor_gpu_regs.h b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
index 7303b7f5ee18..d7cf5165e987 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu_regs.h
+++ b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
@@ -19,6 +19,7 @@
#define GPU_AS_PRESENT 0x18
#define GPU_CSF_ID 0x1C
+#define GPU_INT_BASE 0x20
#define GPU_INT_RAWSTAT 0x20
#define GPU_INT_CLEAR 0x24
#define GPU_INT_MASK 0x28
diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c b/drivers/gpu/drm/panthor/panthor_mmu.c
index b9f6031e24a4..b8665e447d95 100644
--- a/drivers/gpu/drm/panthor/panthor_mmu.c
+++ b/drivers/gpu/drm/panthor/panthor_mmu.c
@@ -584,7 +584,7 @@ static u32 panthor_mmu_as_fault_mask(struct panthor_device *ptdev, u32 as)
/* Forward declaration to call helpers within as_enable/disable */
static void panthor_mmu_irq_handler(struct panthor_device *ptdev, u32 status);
-PANTHOR_IRQ_HANDLER(mmu, MMU, panthor_mmu_irq_handler);
+PANTHOR_IRQ_HANDLER(mmu, panthor_mmu_irq_handler);
static int panthor_mmu_as_enable(struct panthor_device *ptdev, u32 as_nr,
u64 transtab, u64 transcfg, u64 memattr)
@@ -3229,7 +3229,8 @@ int panthor_mmu_init(struct panthor_device *ptdev)
return -ENODEV;
ret = panthor_request_mmu_irq(ptdev, &mmu->irq, irq,
- panthor_mmu_fault_mask(ptdev, ~0));
+ panthor_mmu_fault_mask(ptdev, ~0),
+ MMU_INT_BASE);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/panthor/panthor_mmu_regs.h b/drivers/gpu/drm/panthor/panthor_mmu_regs.h
index cc9cf603cec6..de460042651d 100644
--- a/drivers/gpu/drm/panthor/panthor_mmu_regs.h
+++ b/drivers/gpu/drm/panthor/panthor_mmu_regs.h
@@ -5,6 +5,9 @@
#define __PANTHOR_MMU_REGS_H__
/* MMU regs */
+
+#define MMU_INT_BASE 0x2000
+
#define MMU_INT_RAWSTAT 0x2000
#define MMU_INT_CLEAR 0x2004
#define MMU_INT_MASK 0x2008
diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/panthor/panthor_pwr.c
index aafb0c5c7d23..4f600a6688f9 100644
--- a/drivers/gpu/drm/panthor/panthor_pwr.c
+++ b/drivers/gpu/drm/panthor/panthor_pwr.c
@@ -70,7 +70,7 @@ static void panthor_pwr_irq_handler(struct panthor_device *ptdev, u32 status)
}
spin_unlock(&ptdev->pwr->reqs_lock);
}
-PANTHOR_IRQ_HANDLER(pwr, PWR, panthor_pwr_irq_handler);
+PANTHOR_IRQ_HANDLER(pwr, panthor_pwr_irq_handler);
static void panthor_pwr_write_command(struct panthor_device *ptdev, u32 command, u64 args)
{
@@ -464,7 +464,9 @@ int panthor_pwr_init(struct panthor_device *ptdev)
if (irq < 0)
return irq;
- err = panthor_request_pwr_irq(ptdev, &pwr->irq, irq, PWR_INTERRUPTS_MASK);
+ err = panthor_request_pwr_irq(ptdev, &pwr->irq, irq,
+ PWR_INTERRUPTS_MASK,
+ GPU_CONTROL_BASE + PWR_CONTROL_BASE);
if (err)
return err;
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 4/8] drm/panthor: Store IRQ register base iomem pointer in panthor_irq
2026-04-10 16:46 ` [PATCH 4/8] drm/panthor: Store IRQ register base iomem pointer in panthor_irq Karunika Choo
@ 2026-04-10 17:53 ` Boris Brezillon
0 siblings, 0 replies; 17+ messages in thread
From: Boris Brezillon @ 2026-04-10 17:53 UTC (permalink / raw)
To: Karunika Choo
Cc: dri-devel, nd, Steven Price, Liviu Dudau, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
linux-kernel
On Fri, 10 Apr 2026 17:46:33 +0100
Karunika Choo <karunika.choo@arm.com> wrote:
> static int panthor_request_ ## __name ## _irq(struct panthor_device *ptdev, \
> struct panthor_irq *pirq, \
> - int irq, u32 mask) \
> + int irq, u32 mask, u32 irq_baseaddr) \
Can we pass the void __iomem * directly instead of an offset to apply
to ptdev->iomem?
> { \
> pirq->ptdev = ptdev; \
> pirq->irq = irq; \
> pirq->mask = mask; \
> + pirq->iomem = ptdev->iomem + irq_baseaddr; \
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 5/8] drm/panthor: Use a local iomem base for GPU registers
2026-04-10 16:46 [PATCH 0/8] drm/panthor: Localize register access by component Karunika Choo
` (3 preceding siblings ...)
2026-04-10 16:46 ` [PATCH 4/8] drm/panthor: Store IRQ register base iomem pointer in panthor_irq Karunika Choo
@ 2026-04-10 16:46 ` Karunika Choo
2026-04-10 18:11 ` Boris Brezillon
2026-04-10 16:46 ` [PATCH 6/8] drm/panthor: Use a local iomem base for PWR registers Karunika Choo
` (2 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: Karunika Choo @ 2026-04-10 16:46 UTC (permalink / raw)
To: dri-devel
Cc: nd, Boris Brezillon, Steven Price, Liviu Dudau, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
linux-kernel
Add a GPU_CONTROL-local iomem pointer to struct panthor_gpu and use it
for GPU register accesses.
This limits GPU register accesses to the GPU block instead of using the
device-wide MMIO mapping directly. Interrupt register accesses continue
to use the IRQ-local base provided by the common IRQ helpers.
This is a refactoring only and does not change behaviour.
Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
drivers/gpu/drm/panthor/panthor_gpu.c | 61 +++++++++++++---------
drivers/gpu/drm/panthor/panthor_gpu_regs.h | 6 +--
2 files changed, 38 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c
index 3ddce35ed8b5..abd94de5d15d 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu.c
+++ b/drivers/gpu/drm/panthor/panthor_gpu.c
@@ -29,6 +29,9 @@
* struct panthor_gpu - GPU block management data.
*/
struct panthor_gpu {
+ /** @iomem: CPU mapping of GPU_CONTROL iomem region */
+ void __iomem *iomem;
+
/** @irq: GPU irq. */
struct panthor_irq irq;
@@ -56,12 +59,13 @@ struct panthor_gpu {
static void panthor_gpu_coherency_set(struct panthor_device *ptdev)
{
- gpu_write(ptdev->iomem, GPU_COHERENCY_PROTOCOL,
+ gpu_write(ptdev->gpu->iomem, GPU_COHERENCY_PROTOCOL,
ptdev->gpu_info.selected_coherency);
}
static void panthor_gpu_l2_config_set(struct panthor_device *ptdev)
{
+ struct panthor_gpu *gpu = ptdev->gpu;
const struct panthor_soc_data *data = ptdev->soc_data;
u32 l2_config;
u32 i;
@@ -75,26 +79,28 @@ static void panthor_gpu_l2_config_set(struct panthor_device *ptdev)
}
for (i = 0; i < ARRAY_SIZE(data->asn_hash); i++)
- gpu_write(ptdev->iomem, GPU_ASN_HASH(i), data->asn_hash[i]);
+ gpu_write(gpu->iomem, GPU_ASN_HASH(i), data->asn_hash[i]);
- l2_config = gpu_read(ptdev->iomem, GPU_L2_CONFIG);
+ l2_config = gpu_read(gpu->iomem, GPU_L2_CONFIG);
l2_config |= GPU_L2_CONFIG_ASN_HASH_ENABLE;
- gpu_write(ptdev->iomem, GPU_L2_CONFIG, l2_config);
+ gpu_write(gpu->iomem, GPU_L2_CONFIG, l2_config);
}
static void panthor_gpu_irq_handler(struct panthor_device *ptdev, u32 status)
{
- gpu_write(ptdev->iomem, GPU_INT_CLEAR, status);
+ struct panthor_gpu *gpu = ptdev->gpu;
+
+ gpu_write(gpu->irq.iomem, INT_CLEAR, status);
if (tracepoint_enabled(gpu_power_status) && (status & GPU_POWER_INTERRUPTS_MASK))
trace_gpu_power_status(ptdev->base.dev,
- gpu_read64(ptdev->iomem, SHADER_READY),
- gpu_read64(ptdev->iomem, TILER_READY),
- gpu_read64(ptdev->iomem, L2_READY));
+ gpu_read64(gpu->iomem, SHADER_READY),
+ gpu_read64(gpu->iomem, TILER_READY),
+ gpu_read64(gpu->iomem, L2_READY));
if (status & GPU_IRQ_FAULT) {
- u32 fault_status = gpu_read(ptdev->iomem, GPU_FAULT_STATUS);
- u64 address = gpu_read64(ptdev->iomem, GPU_FAULT_ADDR);
+ u32 fault_status = gpu_read(gpu->iomem, GPU_FAULT_STATUS);
+ u64 address = gpu_read64(gpu->iomem, GPU_FAULT_ADDR);
drm_warn(&ptdev->base, "GPU Fault 0x%08x (%s) at 0x%016llx\n",
fault_status, panthor_exception_name(ptdev, fault_status & 0xFF),
@@ -147,6 +153,7 @@ int panthor_gpu_init(struct panthor_device *ptdev)
if (!gpu)
return -ENOMEM;
+ gpu->iomem = ptdev->iomem + GPU_CONTROL_BASE;
spin_lock_init(&gpu->reqs_lock);
init_waitqueue_head(&gpu->reqs_acked);
mutex_init(&gpu->cache_flush_lock);
@@ -202,10 +209,11 @@ int panthor_gpu_block_power_off(struct panthor_device *ptdev,
u32 pwroff_reg, u32 pwrtrans_reg,
u64 mask, u32 timeout_us)
{
+ struct panthor_gpu *gpu = ptdev->gpu;
u32 val;
int ret;
- ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, pwrtrans_reg, val,
+ ret = gpu_read64_relaxed_poll_timeout(gpu->iomem, pwrtrans_reg, val,
!(mask & val), 100, timeout_us);
if (ret) {
drm_err(&ptdev->base,
@@ -214,9 +222,9 @@ int panthor_gpu_block_power_off(struct panthor_device *ptdev,
return ret;
}
- gpu_write64(ptdev->iomem, pwroff_reg, mask);
+ gpu_write64(gpu->iomem, pwroff_reg, mask);
- ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, pwrtrans_reg, val,
+ ret = gpu_read64_relaxed_poll_timeout(gpu->iomem, pwrtrans_reg, val,
!(mask & val), 100, timeout_us);
if (ret) {
drm_err(&ptdev->base,
@@ -245,10 +253,11 @@ int panthor_gpu_block_power_on(struct panthor_device *ptdev,
u32 pwron_reg, u32 pwrtrans_reg,
u32 rdy_reg, u64 mask, u32 timeout_us)
{
+ struct panthor_gpu *gpu = ptdev->gpu;
u32 val;
int ret;
- ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, pwrtrans_reg, val,
+ ret = gpu_read64_relaxed_poll_timeout(gpu->iomem, pwrtrans_reg, val,
!(mask & val), 100, timeout_us);
if (ret) {
drm_err(&ptdev->base,
@@ -257,9 +266,9 @@ int panthor_gpu_block_power_on(struct panthor_device *ptdev,
return ret;
}
- gpu_write64(ptdev->iomem, pwron_reg, mask);
+ gpu_write64(gpu->iomem, pwron_reg, mask);
- ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, rdy_reg, val,
+ ret = gpu_read64_relaxed_poll_timeout(gpu->iomem, rdy_reg, val,
(mask & val) == val,
100, timeout_us);
if (ret) {
@@ -318,6 +327,7 @@ int panthor_gpu_l2_power_on(struct panthor_device *ptdev)
int panthor_gpu_flush_caches(struct panthor_device *ptdev,
u32 l2, u32 lsc, u32 other)
{
+ struct panthor_gpu *gpu = ptdev->gpu;
unsigned long flags;
int ret = 0;
@@ -327,7 +337,7 @@ int panthor_gpu_flush_caches(struct panthor_device *ptdev,
spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
if (!(ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED)) {
ptdev->gpu->pending_reqs |= GPU_IRQ_CLEAN_CACHES_COMPLETED;
- gpu_write(ptdev->iomem, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other));
+ gpu_write(gpu->iomem, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other));
} else {
ret = -EIO;
}
@@ -341,7 +351,7 @@ int panthor_gpu_flush_caches(struct panthor_device *ptdev,
msecs_to_jiffies(100))) {
spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
if ((ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED) != 0 &&
- !(gpu_read(ptdev->iomem, GPU_INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED))
+ !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED))
ret = -ETIMEDOUT;
else
ptdev->gpu->pending_reqs &= ~GPU_IRQ_CLEAN_CACHES_COMPLETED;
@@ -364,6 +374,7 @@ int panthor_gpu_flush_caches(struct panthor_device *ptdev,
*/
int panthor_gpu_soft_reset(struct panthor_device *ptdev)
{
+ struct panthor_gpu *gpu = ptdev->gpu;
bool timedout = false;
unsigned long flags;
@@ -371,8 +382,8 @@ int panthor_gpu_soft_reset(struct panthor_device *ptdev)
if (!drm_WARN_ON(&ptdev->base,
ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED)) {
ptdev->gpu->pending_reqs |= GPU_IRQ_RESET_COMPLETED;
- gpu_write(ptdev->iomem, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED);
- gpu_write(ptdev->iomem, GPU_CMD, GPU_SOFT_RESET);
+ gpu_write(gpu->irq.iomem, INT_CLEAR, GPU_IRQ_RESET_COMPLETED);
+ gpu_write(gpu->iomem, GPU_CMD, GPU_SOFT_RESET);
}
spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags);
@@ -381,7 +392,7 @@ int panthor_gpu_soft_reset(struct panthor_device *ptdev)
msecs_to_jiffies(100))) {
spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
if ((ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED) != 0 &&
- !(gpu_read(ptdev->iomem, GPU_INT_RAWSTAT) & GPU_IRQ_RESET_COMPLETED))
+ !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) & GPU_IRQ_RESET_COMPLETED))
timedout = true;
else
ptdev->gpu->pending_reqs &= ~GPU_IRQ_RESET_COMPLETED;
@@ -430,17 +441,17 @@ void panthor_gpu_resume(struct panthor_device *ptdev)
u64 panthor_gpu_get_timestap(struct panthor_device *ptdev)
{
- return gpu_read64_counter(ptdev->iomem, GPU_TIMESTAMP);
+ return gpu_read64_counter(ptdev->gpu->iomem, GPU_TIMESTAMP);
}
u64 panthor_gpu_get_timestap_offset(struct panthor_device *ptdev)
{
- return gpu_read64(ptdev->iomem, GPU_TIMESTAMP_OFFSET);
+ return gpu_read64(ptdev->gpu->iomem, GPU_TIMESTAMP_OFFSET);
}
u64 panthor_gpu_get_cycle_count(struct panthor_device *ptdev)
{
- return gpu_read64_counter(ptdev->iomem, GPU_CYCLE_COUNT);
+ return gpu_read64_counter(ptdev->gpu->iomem, GPU_CYCLE_COUNT);
}
int panthor_gpu_coherency_init(struct panthor_device *ptdev)
@@ -459,7 +470,7 @@ int panthor_gpu_coherency_init(struct panthor_device *ptdev)
/* Check if the ACE-Lite coherency protocol is actually supported by the GPU.
* ACE protocol has never been supported for command stream frontend GPUs.
*/
- if ((gpu_read(ptdev->iomem, GPU_COHERENCY_FEATURES) &
+ if ((gpu_read(ptdev->gpu->iomem, GPU_COHERENCY_FEATURES) &
GPU_COHERENCY_PROT_BIT(ACE_LITE))) {
ptdev->gpu_info.selected_coherency = GPU_COHERENCY_ACE_LITE;
return 0;
diff --git a/drivers/gpu/drm/panthor/panthor_gpu_regs.h b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
index d7cf5165e987..f64e7661f765 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu_regs.h
+++ b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
@@ -4,6 +4,8 @@
#ifndef __PANTHOR_GPU_REGS_H__
#define __PANTHOR_GPU_REGS_H__
+#define GPU_CONTROL_BASE 0x0
+
#define GPU_L2_FEATURES 0x4
#define GPU_L2_FEATURES_LINE_SIZE(x) (1 << ((x) & GENMASK(7, 0)))
@@ -20,10 +22,6 @@
#define GPU_CSF_ID 0x1C
#define GPU_INT_BASE 0x20
-#define GPU_INT_RAWSTAT 0x20
-#define GPU_INT_CLEAR 0x24
-#define GPU_INT_MASK 0x28
-#define GPU_INT_STAT 0x2c
#define GPU_IRQ_FAULT BIT(0)
#define GPU_IRQ_PROTM_FAULT BIT(1)
#define GPU_IRQ_RESET_COMPLETED BIT(8)
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 5/8] drm/panthor: Use a local iomem base for GPU registers
2026-04-10 16:46 ` [PATCH 5/8] drm/panthor: Use a local iomem base for GPU registers Karunika Choo
@ 2026-04-10 18:11 ` Boris Brezillon
0 siblings, 0 replies; 17+ messages in thread
From: Boris Brezillon @ 2026-04-10 18:11 UTC (permalink / raw)
To: Karunika Choo
Cc: dri-devel, nd, Steven Price, Liviu Dudau, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
linux-kernel
On Fri, 10 Apr 2026 17:46:34 +0100
Karunika Choo <karunika.choo@arm.com> wrote:
> Add a GPU_CONTROL-local iomem pointer to struct panthor_gpu and use it
> for GPU register accesses.
>
> This limits GPU register accesses to the GPU block instead of using the
> device-wide MMIO mapping directly. Interrupt register accesses continue
> to use the IRQ-local base provided by the common IRQ helpers.
>
> This is a refactoring only and does not change behaviour.
>
> Signed-off-by: Karunika Choo <karunika.choo@arm.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
> ---
> drivers/gpu/drm/panthor/panthor_gpu.c | 61 +++++++++++++---------
> drivers/gpu/drm/panthor/panthor_gpu_regs.h | 6 +--
> 2 files changed, 38 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c
> index 3ddce35ed8b5..abd94de5d15d 100644
> --- a/drivers/gpu/drm/panthor/panthor_gpu.c
> +++ b/drivers/gpu/drm/panthor/panthor_gpu.c
> @@ -29,6 +29,9 @@
> * struct panthor_gpu - GPU block management data.
> */
> struct panthor_gpu {
> + /** @iomem: CPU mapping of GPU_CONTROL iomem region */
> + void __iomem *iomem;
> +
> /** @irq: GPU irq. */
> struct panthor_irq irq;
>
> @@ -56,12 +59,13 @@ struct panthor_gpu {
>
> static void panthor_gpu_coherency_set(struct panthor_device *ptdev)
> {
> - gpu_write(ptdev->iomem, GPU_COHERENCY_PROTOCOL,
> + gpu_write(ptdev->gpu->iomem, GPU_COHERENCY_PROTOCOL,
> ptdev->gpu_info.selected_coherency);
> }
>
> static void panthor_gpu_l2_config_set(struct panthor_device *ptdev)
> {
> + struct panthor_gpu *gpu = ptdev->gpu;
> const struct panthor_soc_data *data = ptdev->soc_data;
> u32 l2_config;
> u32 i;
> @@ -75,26 +79,28 @@ static void panthor_gpu_l2_config_set(struct panthor_device *ptdev)
> }
>
> for (i = 0; i < ARRAY_SIZE(data->asn_hash); i++)
> - gpu_write(ptdev->iomem, GPU_ASN_HASH(i), data->asn_hash[i]);
> + gpu_write(gpu->iomem, GPU_ASN_HASH(i), data->asn_hash[i]);
>
> - l2_config = gpu_read(ptdev->iomem, GPU_L2_CONFIG);
> + l2_config = gpu_read(gpu->iomem, GPU_L2_CONFIG);
> l2_config |= GPU_L2_CONFIG_ASN_HASH_ENABLE;
> - gpu_write(ptdev->iomem, GPU_L2_CONFIG, l2_config);
> + gpu_write(gpu->iomem, GPU_L2_CONFIG, l2_config);
> }
>
> static void panthor_gpu_irq_handler(struct panthor_device *ptdev, u32 status)
> {
> - gpu_write(ptdev->iomem, GPU_INT_CLEAR, status);
> + struct panthor_gpu *gpu = ptdev->gpu;
> +
> + gpu_write(gpu->irq.iomem, INT_CLEAR, status);
>
> if (tracepoint_enabled(gpu_power_status) && (status & GPU_POWER_INTERRUPTS_MASK))
> trace_gpu_power_status(ptdev->base.dev,
> - gpu_read64(ptdev->iomem, SHADER_READY),
> - gpu_read64(ptdev->iomem, TILER_READY),
> - gpu_read64(ptdev->iomem, L2_READY));
> + gpu_read64(gpu->iomem, SHADER_READY),
> + gpu_read64(gpu->iomem, TILER_READY),
> + gpu_read64(gpu->iomem, L2_READY));
>
> if (status & GPU_IRQ_FAULT) {
> - u32 fault_status = gpu_read(ptdev->iomem, GPU_FAULT_STATUS);
> - u64 address = gpu_read64(ptdev->iomem, GPU_FAULT_ADDR);
> + u32 fault_status = gpu_read(gpu->iomem, GPU_FAULT_STATUS);
> + u64 address = gpu_read64(gpu->iomem, GPU_FAULT_ADDR);
>
> drm_warn(&ptdev->base, "GPU Fault 0x%08x (%s) at 0x%016llx\n",
> fault_status, panthor_exception_name(ptdev, fault_status & 0xFF),
> @@ -147,6 +153,7 @@ int panthor_gpu_init(struct panthor_device *ptdev)
> if (!gpu)
> return -ENOMEM;
>
> + gpu->iomem = ptdev->iomem + GPU_CONTROL_BASE;
> spin_lock_init(&gpu->reqs_lock);
> init_waitqueue_head(&gpu->reqs_acked);
> mutex_init(&gpu->cache_flush_lock);
> @@ -202,10 +209,11 @@ int panthor_gpu_block_power_off(struct panthor_device *ptdev,
> u32 pwroff_reg, u32 pwrtrans_reg,
> u64 mask, u32 timeout_us)
> {
> + struct panthor_gpu *gpu = ptdev->gpu;
> u32 val;
> int ret;
>
> - ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, pwrtrans_reg, val,
> + ret = gpu_read64_relaxed_poll_timeout(gpu->iomem, pwrtrans_reg, val,
> !(mask & val), 100, timeout_us);
> if (ret) {
> drm_err(&ptdev->base,
> @@ -214,9 +222,9 @@ int panthor_gpu_block_power_off(struct panthor_device *ptdev,
> return ret;
> }
>
> - gpu_write64(ptdev->iomem, pwroff_reg, mask);
> + gpu_write64(gpu->iomem, pwroff_reg, mask);
>
> - ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, pwrtrans_reg, val,
> + ret = gpu_read64_relaxed_poll_timeout(gpu->iomem, pwrtrans_reg, val,
> !(mask & val), 100, timeout_us);
> if (ret) {
> drm_err(&ptdev->base,
> @@ -245,10 +253,11 @@ int panthor_gpu_block_power_on(struct panthor_device *ptdev,
> u32 pwron_reg, u32 pwrtrans_reg,
> u32 rdy_reg, u64 mask, u32 timeout_us)
> {
> + struct panthor_gpu *gpu = ptdev->gpu;
> u32 val;
> int ret;
>
> - ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, pwrtrans_reg, val,
> + ret = gpu_read64_relaxed_poll_timeout(gpu->iomem, pwrtrans_reg, val,
> !(mask & val), 100, timeout_us);
> if (ret) {
> drm_err(&ptdev->base,
> @@ -257,9 +266,9 @@ int panthor_gpu_block_power_on(struct panthor_device *ptdev,
> return ret;
> }
>
> - gpu_write64(ptdev->iomem, pwron_reg, mask);
> + gpu_write64(gpu->iomem, pwron_reg, mask);
>
> - ret = gpu_read64_relaxed_poll_timeout(ptdev->iomem, rdy_reg, val,
> + ret = gpu_read64_relaxed_poll_timeout(gpu->iomem, rdy_reg, val,
> (mask & val) == val,
> 100, timeout_us);
> if (ret) {
> @@ -318,6 +327,7 @@ int panthor_gpu_l2_power_on(struct panthor_device *ptdev)
> int panthor_gpu_flush_caches(struct panthor_device *ptdev,
> u32 l2, u32 lsc, u32 other)
> {
> + struct panthor_gpu *gpu = ptdev->gpu;
> unsigned long flags;
> int ret = 0;
>
> @@ -327,7 +337,7 @@ int panthor_gpu_flush_caches(struct panthor_device *ptdev,
> spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
> if (!(ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED)) {
> ptdev->gpu->pending_reqs |= GPU_IRQ_CLEAN_CACHES_COMPLETED;
> - gpu_write(ptdev->iomem, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other));
> + gpu_write(gpu->iomem, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other));
> } else {
> ret = -EIO;
> }
> @@ -341,7 +351,7 @@ int panthor_gpu_flush_caches(struct panthor_device *ptdev,
> msecs_to_jiffies(100))) {
> spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
> if ((ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED) != 0 &&
> - !(gpu_read(ptdev->iomem, GPU_INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED))
> + !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED))
> ret = -ETIMEDOUT;
> else
> ptdev->gpu->pending_reqs &= ~GPU_IRQ_CLEAN_CACHES_COMPLETED;
> @@ -364,6 +374,7 @@ int panthor_gpu_flush_caches(struct panthor_device *ptdev,
> */
> int panthor_gpu_soft_reset(struct panthor_device *ptdev)
> {
> + struct panthor_gpu *gpu = ptdev->gpu;
> bool timedout = false;
> unsigned long flags;
>
> @@ -371,8 +382,8 @@ int panthor_gpu_soft_reset(struct panthor_device *ptdev)
> if (!drm_WARN_ON(&ptdev->base,
> ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED)) {
> ptdev->gpu->pending_reqs |= GPU_IRQ_RESET_COMPLETED;
> - gpu_write(ptdev->iomem, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED);
> - gpu_write(ptdev->iomem, GPU_CMD, GPU_SOFT_RESET);
> + gpu_write(gpu->irq.iomem, INT_CLEAR, GPU_IRQ_RESET_COMPLETED);
> + gpu_write(gpu->iomem, GPU_CMD, GPU_SOFT_RESET);
> }
> spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags);
>
> @@ -381,7 +392,7 @@ int panthor_gpu_soft_reset(struct panthor_device *ptdev)
> msecs_to_jiffies(100))) {
> spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags);
> if ((ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED) != 0 &&
> - !(gpu_read(ptdev->iomem, GPU_INT_RAWSTAT) & GPU_IRQ_RESET_COMPLETED))
> + !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) & GPU_IRQ_RESET_COMPLETED))
> timedout = true;
> else
> ptdev->gpu->pending_reqs &= ~GPU_IRQ_RESET_COMPLETED;
> @@ -430,17 +441,17 @@ void panthor_gpu_resume(struct panthor_device *ptdev)
>
> u64 panthor_gpu_get_timestap(struct panthor_device *ptdev)
> {
> - return gpu_read64_counter(ptdev->iomem, GPU_TIMESTAMP);
> + return gpu_read64_counter(ptdev->gpu->iomem, GPU_TIMESTAMP);
> }
>
> u64 panthor_gpu_get_timestap_offset(struct panthor_device *ptdev)
> {
> - return gpu_read64(ptdev->iomem, GPU_TIMESTAMP_OFFSET);
> + return gpu_read64(ptdev->gpu->iomem, GPU_TIMESTAMP_OFFSET);
> }
>
> u64 panthor_gpu_get_cycle_count(struct panthor_device *ptdev)
> {
> - return gpu_read64_counter(ptdev->iomem, GPU_CYCLE_COUNT);
> + return gpu_read64_counter(ptdev->gpu->iomem, GPU_CYCLE_COUNT);
> }
>
> int panthor_gpu_coherency_init(struct panthor_device *ptdev)
> @@ -459,7 +470,7 @@ int panthor_gpu_coherency_init(struct panthor_device *ptdev)
> /* Check if the ACE-Lite coherency protocol is actually supported by the GPU.
> * ACE protocol has never been supported for command stream frontend GPUs.
> */
> - if ((gpu_read(ptdev->iomem, GPU_COHERENCY_FEATURES) &
> + if ((gpu_read(ptdev->gpu->iomem, GPU_COHERENCY_FEATURES) &
> GPU_COHERENCY_PROT_BIT(ACE_LITE))) {
> ptdev->gpu_info.selected_coherency = GPU_COHERENCY_ACE_LITE;
> return 0;
> diff --git a/drivers/gpu/drm/panthor/panthor_gpu_regs.h b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
> index d7cf5165e987..f64e7661f765 100644
> --- a/drivers/gpu/drm/panthor/panthor_gpu_regs.h
> +++ b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
> @@ -4,6 +4,8 @@
> #ifndef __PANTHOR_GPU_REGS_H__
> #define __PANTHOR_GPU_REGS_H__
>
> +#define GPU_CONTROL_BASE 0x0
> +
> #define GPU_L2_FEATURES 0x4
> #define GPU_L2_FEATURES_LINE_SIZE(x) (1 << ((x) & GENMASK(7, 0)))
>
> @@ -20,10 +22,6 @@
> #define GPU_CSF_ID 0x1C
>
> #define GPU_INT_BASE 0x20
> -#define GPU_INT_RAWSTAT 0x20
> -#define GPU_INT_CLEAR 0x24
> -#define GPU_INT_MASK 0x28
> -#define GPU_INT_STAT 0x2c
> #define GPU_IRQ_FAULT BIT(0)
> #define GPU_IRQ_PROTM_FAULT BIT(1)
> #define GPU_IRQ_RESET_COMPLETED BIT(8)
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 6/8] drm/panthor: Use a local iomem base for PWR registers
2026-04-10 16:46 [PATCH 0/8] drm/panthor: Localize register access by component Karunika Choo
` (4 preceding siblings ...)
2026-04-10 16:46 ` [PATCH 5/8] drm/panthor: Use a local iomem base for GPU registers Karunika Choo
@ 2026-04-10 16:46 ` Karunika Choo
2026-04-10 18:12 ` Boris Brezillon
2026-04-10 16:46 ` [PATCH 7/8] drm/panthor: Use a local iomem base for firmware control registers Karunika Choo
2026-04-10 16:46 ` [PATCH 8/8] drm/panthor: Use a local iomem base for MMU AS registers Karunika Choo
7 siblings, 1 reply; 17+ messages in thread
From: Karunika Choo @ 2026-04-10 16:46 UTC (permalink / raw)
To: dri-devel
Cc: nd, Boris Brezillon, Steven Price, Liviu Dudau, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
linux-kernel
Add a PWR_CONTROL-local iomem pointer to struct panthor_pwr and switch
power controller register accesses to that base.
Keep interrupt register accesses on the IRQ-local iomem base and update
the register definitions so the PWR block can be addressed relative to
its local base. This removes the remaining dependence on the global
device MMIO mapping for PWR register accesses.
No functional change intended.
Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
drivers/gpu/drm/panthor/panthor_pwr.c | 79 ++++++++++++++--------
drivers/gpu/drm/panthor/panthor_pwr_regs.h | 50 +++++++-------
2 files changed, 74 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/panthor/panthor_pwr.c
index 4f600a6688f9..f7fdbd15abf9 100644
--- a/drivers/gpu/drm/panthor/panthor_pwr.c
+++ b/drivers/gpu/drm/panthor/panthor_pwr.c
@@ -40,6 +40,9 @@
* struct panthor_pwr - PWR_CONTROL block management data.
*/
struct panthor_pwr {
+ /** @iomem: CPU mapping of PWR_CONTROL iomem region */
+ void __iomem *iomem;
+
/** @irq: PWR irq. */
struct panthor_irq irq;
@@ -55,8 +58,10 @@ struct panthor_pwr {
static void panthor_pwr_irq_handler(struct panthor_device *ptdev, u32 status)
{
+ struct panthor_pwr *pwr = ptdev->pwr;
+
spin_lock(&ptdev->pwr->reqs_lock);
- gpu_write(ptdev->iomem, PWR_INT_CLEAR, status);
+ gpu_write(pwr->irq.iomem, INT_CLEAR, status);
if (unlikely(status & PWR_IRQ_COMMAND_NOT_ALLOWED))
drm_err(&ptdev->base, "PWR_IRQ: COMMAND_NOT_ALLOWED");
@@ -74,15 +79,19 @@ PANTHOR_IRQ_HANDLER(pwr, panthor_pwr_irq_handler);
static void panthor_pwr_write_command(struct panthor_device *ptdev, u32 command, u64 args)
{
+ struct panthor_pwr *pwr = ptdev->pwr;
+
if (args)
- gpu_write64(ptdev->iomem, PWR_CMDARG, args);
+ gpu_write64(pwr->iomem, PWR_CMDARG, args);
- gpu_write(ptdev->iomem, PWR_COMMAND, command);
+ gpu_write(pwr->iomem, PWR_COMMAND, command);
}
static bool reset_irq_raised(struct panthor_device *ptdev)
{
- return gpu_read(ptdev->iomem, PWR_INT_RAWSTAT) & PWR_IRQ_RESET_COMPLETED;
+ struct panthor_pwr *pwr = ptdev->pwr;
+
+ return gpu_read(pwr->irq.iomem, INT_RAWSTAT) & PWR_IRQ_RESET_COMPLETED;
}
static bool reset_pending(struct panthor_device *ptdev)
@@ -92,12 +101,14 @@ static bool reset_pending(struct panthor_device *ptdev)
static int panthor_pwr_reset(struct panthor_device *ptdev, u32 reset_cmd)
{
+ struct panthor_pwr *pwr = ptdev->pwr;
+
scoped_guard(spinlock_irqsave, &ptdev->pwr->reqs_lock) {
if (reset_pending(ptdev)) {
drm_WARN(&ptdev->base, 1, "Reset already pending");
} else {
ptdev->pwr->pending_reqs |= PWR_IRQ_RESET_COMPLETED;
- gpu_write(ptdev->iomem, PWR_INT_CLEAR, PWR_IRQ_RESET_COMPLETED);
+ gpu_write(pwr->irq.iomem, INT_CLEAR, PWR_IRQ_RESET_COMPLETED);
panthor_pwr_write_command(ptdev, reset_cmd, 0);
}
}
@@ -182,11 +193,12 @@ static u8 get_domain_subdomain(struct panthor_device *ptdev, u32 domain)
static int panthor_pwr_domain_wait_transition(struct panthor_device *ptdev, u32 domain,
u32 timeout_us)
{
+ struct panthor_pwr *pwr = ptdev->pwr;
u32 pwrtrans_reg = get_domain_pwrtrans_reg(domain);
u64 val;
int ret = 0;
- ret = gpu_read64_poll_timeout(ptdev->iomem, pwrtrans_reg, val, !(PWR_ALL_CORES_MASK & val), 100,
+ ret = gpu_read64_poll_timeout(pwr->iomem, pwrtrans_reg, val, !(PWR_ALL_CORES_MASK & val), 100,
timeout_us);
if (ret) {
drm_err(&ptdev->base, "%s domain power in transition, pwrtrans(0x%llx)",
@@ -199,22 +211,25 @@ static int panthor_pwr_domain_wait_transition(struct panthor_device *ptdev, u32
static void panthor_pwr_debug_info_show(struct panthor_device *ptdev)
{
+ struct panthor_pwr *pwr = ptdev->pwr;
+
drm_info(&ptdev->base, "GPU_FEATURES: 0x%016llx", ptdev->gpu_info.gpu_features);
- drm_info(&ptdev->base, "PWR_STATUS: 0x%016llx", gpu_read64(ptdev->iomem, PWR_STATUS));
- drm_info(&ptdev->base, "L2_PRESENT: 0x%016llx", gpu_read64(ptdev->iomem, PWR_L2_PRESENT));
- drm_info(&ptdev->base, "L2_PWRTRANS: 0x%016llx", gpu_read64(ptdev->iomem, PWR_L2_PWRTRANS));
- drm_info(&ptdev->base, "L2_READY: 0x%016llx", gpu_read64(ptdev->iomem, PWR_L2_READY));
- drm_info(&ptdev->base, "TILER_PRESENT: 0x%016llx", gpu_read64(ptdev->iomem, PWR_TILER_PRESENT));
- drm_info(&ptdev->base, "TILER_PWRTRANS: 0x%016llx", gpu_read64(ptdev->iomem, PWR_TILER_PWRTRANS));
- drm_info(&ptdev->base, "TILER_READY: 0x%016llx", gpu_read64(ptdev->iomem, PWR_TILER_READY));
- drm_info(&ptdev->base, "SHADER_PRESENT: 0x%016llx", gpu_read64(ptdev->iomem, PWR_SHADER_PRESENT));
- drm_info(&ptdev->base, "SHADER_PWRTRANS: 0x%016llx", gpu_read64(ptdev->iomem, PWR_SHADER_PWRTRANS));
- drm_info(&ptdev->base, "SHADER_READY: 0x%016llx", gpu_read64(ptdev->iomem, PWR_SHADER_READY));
+ drm_info(&ptdev->base, "PWR_STATUS: 0x%016llx", gpu_read64(pwr->iomem, PWR_STATUS));
+ drm_info(&ptdev->base, "L2_PRESENT: 0x%016llx", gpu_read64(pwr->iomem, PWR_L2_PRESENT));
+ drm_info(&ptdev->base, "L2_PWRTRANS: 0x%016llx", gpu_read64(pwr->iomem, PWR_L2_PWRTRANS));
+ drm_info(&ptdev->base, "L2_READY: 0x%016llx", gpu_read64(pwr->iomem, PWR_L2_READY));
+ drm_info(&ptdev->base, "TILER_PRESENT: 0x%016llx", gpu_read64(pwr->iomem, PWR_TILER_PRESENT));
+ drm_info(&ptdev->base, "TILER_PWRTRANS: 0x%016llx", gpu_read64(pwr->iomem, PWR_TILER_PWRTRANS));
+ drm_info(&ptdev->base, "TILER_READY: 0x%016llx", gpu_read64(pwr->iomem, PWR_TILER_READY));
+ drm_info(&ptdev->base, "SHADER_PRESENT: 0x%016llx", gpu_read64(pwr->iomem, PWR_SHADER_PRESENT));
+ drm_info(&ptdev->base, "SHADER_PWRTRANS: 0x%016llx", gpu_read64(pwr->iomem, PWR_SHADER_PWRTRANS));
+ drm_info(&ptdev->base, "SHADER_READY: 0x%016llx", gpu_read64(pwr->iomem, PWR_SHADER_READY));
}
static int panthor_pwr_domain_transition(struct panthor_device *ptdev, u32 cmd, u32 domain,
u64 mask, u32 timeout_us)
{
+ struct panthor_pwr *pwr = ptdev->pwr;
u32 ready_reg = get_domain_ready_reg(domain);
u32 pwr_cmd = PWR_COMMAND_DEF(cmd, domain, get_domain_subdomain(ptdev, domain));
u64 expected_val = 0;
@@ -241,12 +256,12 @@ static int panthor_pwr_domain_transition(struct panthor_device *ptdev, u32 cmd,
return ret;
/* domain already in target state, return early */
- if ((gpu_read64(ptdev->iomem, ready_reg) & mask) == expected_val)
+ if ((gpu_read64(pwr->iomem, ready_reg) & mask) == expected_val)
return 0;
panthor_pwr_write_command(ptdev, pwr_cmd, mask);
- ret = gpu_read64_poll_timeout(ptdev->iomem, ready_reg, val, (mask & val) == expected_val,
+ ret = gpu_read64_poll_timeout(pwr->iomem, ready_reg, val, (mask & val) == expected_val,
100, timeout_us);
if (ret) {
drm_err(&ptdev->base,
@@ -279,8 +294,9 @@ static int panthor_pwr_domain_transition(struct panthor_device *ptdev, u32 cmd,
*/
static int retract_domain(struct panthor_device *ptdev, u32 domain)
{
+ struct panthor_pwr *pwr = ptdev->pwr;
const u32 pwr_cmd = PWR_COMMAND_DEF(PWR_COMMAND_RETRACT, domain, 0);
- const u64 pwr_status = gpu_read64(ptdev->iomem, PWR_STATUS);
+ const u64 pwr_status = gpu_read64(pwr->iomem, PWR_STATUS);
const u64 delegated_mask = PWR_STATUS_DOMAIN_DELEGATED(domain);
const u64 allow_mask = PWR_STATUS_DOMAIN_ALLOWED(domain);
u64 val;
@@ -289,7 +305,7 @@ static int retract_domain(struct panthor_device *ptdev, u32 domain)
if (drm_WARN_ON(&ptdev->base, domain == PWR_COMMAND_DOMAIN_L2))
return -EPERM;
- ret = gpu_read64_poll_timeout(ptdev->iomem, PWR_STATUS, val,
+ ret = gpu_read64_poll_timeout(pwr->iomem, PWR_STATUS, val,
!(PWR_STATUS_RETRACT_PENDING & val), 0,
PWR_RETRACT_TIMEOUT_US);
if (ret) {
@@ -308,7 +324,7 @@ static int retract_domain(struct panthor_device *ptdev, u32 domain)
* On successful retraction
* allow-flag will be set with delegated-flag being cleared.
*/
- ret = gpu_read64_poll_timeout(ptdev->iomem, PWR_STATUS, val,
+ ret = gpu_read64_poll_timeout(pwr->iomem, PWR_STATUS, val,
((delegated_mask | allow_mask) & val) == allow_mask, 10,
PWR_TRANSITION_TIMEOUT_US);
if (ret) {
@@ -334,8 +350,9 @@ static int retract_domain(struct panthor_device *ptdev, u32 domain)
*/
static int delegate_domain(struct panthor_device *ptdev, u32 domain)
{
+ struct panthor_pwr *pwr = ptdev->pwr;
const u32 pwr_cmd = PWR_COMMAND_DEF(PWR_COMMAND_DELEGATE, domain, 0);
- const u64 pwr_status = gpu_read64(ptdev->iomem, PWR_STATUS);
+ const u64 pwr_status = gpu_read64(pwr->iomem, PWR_STATUS);
const u64 allow_mask = PWR_STATUS_DOMAIN_ALLOWED(domain);
const u64 delegated_mask = PWR_STATUS_DOMAIN_DELEGATED(domain);
u64 val;
@@ -364,7 +381,7 @@ static int delegate_domain(struct panthor_device *ptdev, u32 domain)
* On successful delegation
* allow-flag will be cleared with delegated-flag being set.
*/
- ret = gpu_read64_poll_timeout(ptdev->iomem, PWR_STATUS, val,
+ ret = gpu_read64_poll_timeout(pwr->iomem, PWR_STATUS, val,
((delegated_mask | allow_mask) & val) == delegated_mask,
10, PWR_TRANSITION_TIMEOUT_US);
if (ret) {
@@ -412,7 +429,8 @@ static int panthor_pwr_delegate_domains(struct panthor_device *ptdev)
*/
static int panthor_pwr_domain_force_off(struct panthor_device *ptdev, u32 domain)
{
- const u64 domain_ready = gpu_read64(ptdev->iomem, get_domain_ready_reg(domain));
+ struct panthor_pwr *pwr = ptdev->pwr;
+ const u64 domain_ready = gpu_read64(pwr->iomem, get_domain_ready_reg(domain));
int ret;
/* Domain already powered down, early exit. */
@@ -456,6 +474,7 @@ int panthor_pwr_init(struct panthor_device *ptdev)
if (!pwr)
return -ENOMEM;
+ pwr->iomem = ptdev->iomem + GPU_CONTROL_BASE + PWR_CONTROL_BASE;
spin_lock_init(&pwr->reqs_lock);
init_waitqueue_head(&pwr->reqs_acked);
ptdev->pwr = pwr;
@@ -466,7 +485,7 @@ int panthor_pwr_init(struct panthor_device *ptdev)
err = panthor_request_pwr_irq(ptdev, &pwr->irq, irq,
PWR_INTERRUPTS_MASK,
- GPU_CONTROL_BASE + PWR_CONTROL_BASE);
+ GPU_CONTROL_BASE + PWR_INT_BASE);
if (err)
return err;
@@ -475,7 +494,9 @@ int panthor_pwr_init(struct panthor_device *ptdev)
int panthor_pwr_reset_soft(struct panthor_device *ptdev)
{
- if (!(gpu_read64(ptdev->iomem, PWR_STATUS) & PWR_STATUS_ALLOW_SOFT_RESET)) {
+ struct panthor_pwr *pwr = ptdev->pwr;
+
+ if (!(gpu_read64(pwr->iomem, PWR_STATUS) & PWR_STATUS_ALLOW_SOFT_RESET)) {
drm_err(&ptdev->base, "RESET_SOFT not allowed");
return -EOPNOTSUPP;
}
@@ -485,8 +506,9 @@ int panthor_pwr_reset_soft(struct panthor_device *ptdev)
void panthor_pwr_l2_power_off(struct panthor_device *ptdev)
{
+ struct panthor_pwr *pwr = ptdev->pwr;
const u64 l2_allow_mask = PWR_STATUS_DOMAIN_ALLOWED(PWR_COMMAND_DOMAIN_L2);
- const u64 pwr_status = gpu_read64(ptdev->iomem, PWR_STATUS);
+ const u64 pwr_status = gpu_read64(pwr->iomem, PWR_STATUS);
/* Abort if L2 power off constraints are not satisfied */
if (!(pwr_status & l2_allow_mask)) {
@@ -512,7 +534,8 @@ void panthor_pwr_l2_power_off(struct panthor_device *ptdev)
int panthor_pwr_l2_power_on(struct panthor_device *ptdev)
{
- const u32 pwr_status = gpu_read64(ptdev->iomem, PWR_STATUS);
+ struct panthor_pwr *pwr = ptdev->pwr;
+ const u32 pwr_status = gpu_read64(pwr->iomem, PWR_STATUS);
const u32 l2_allow_mask = PWR_STATUS_DOMAIN_ALLOWED(PWR_COMMAND_DOMAIN_L2);
int ret;
diff --git a/drivers/gpu/drm/panthor/panthor_pwr_regs.h b/drivers/gpu/drm/panthor/panthor_pwr_regs.h
index ad3e446971db..1fce05c3a96e 100644
--- a/drivers/gpu/drm/panthor/panthor_pwr_regs.h
+++ b/drivers/gpu/drm/panthor/panthor_pwr_regs.h
@@ -5,12 +5,8 @@
#define __PANTHOR_PWR_REGS_H__
#define PWR_CONTROL_BASE 0x800
-#define PWR_CTRL_REG(x) (PWR_CONTROL_BASE + (x))
-#define PWR_INT_RAWSTAT PWR_CTRL_REG(0x0)
-#define PWR_INT_CLEAR PWR_CTRL_REG(0x4)
-#define PWR_INT_MASK PWR_CTRL_REG(0x8)
-#define PWR_INT_STAT PWR_CTRL_REG(0xc)
+#define PWR_INT_BASE 0x800
#define PWR_IRQ_POWER_CHANGED_SINGLE BIT(0)
#define PWR_IRQ_POWER_CHANGED_ALL BIT(1)
#define PWR_IRQ_DELEGATION_CHANGED BIT(2)
@@ -20,7 +16,7 @@
#define PWR_IRQ_COMMAND_NOT_ALLOWED BIT(30)
#define PWR_IRQ_COMMAND_INVALID BIT(31)
-#define PWR_STATUS PWR_CTRL_REG(0x20)
+#define PWR_STATUS 0x20
#define PWR_STATUS_ALLOW_L2 BIT_U64(0)
#define PWR_STATUS_ALLOW_TILER BIT_U64(1)
#define PWR_STATUS_ALLOW_SHADER BIT_U64(8)
@@ -41,7 +37,7 @@
#define PWR_STATUS_RETRACT_PENDING BIT_U64(43)
#define PWR_STATUS_INSPECT_PENDING BIT_U64(44)
-#define PWR_COMMAND PWR_CTRL_REG(0x28)
+#define PWR_COMMAND 0x28
#define PWR_COMMAND_POWER_UP 0x10
#define PWR_COMMAND_POWER_DOWN 0x11
#define PWR_COMMAND_DELEGATE 0x20
@@ -58,26 +54,26 @@
#define PWR_COMMAND_DEF(cmd, domain, subdomain) \
(((subdomain) << 16) | ((domain) << 8) | (cmd))
-#define PWR_CMDARG PWR_CTRL_REG(0x30)
+#define PWR_CMDARG 0x30
-#define PWR_L2_PRESENT PWR_CTRL_REG(0x100)
-#define PWR_L2_READY PWR_CTRL_REG(0x108)
-#define PWR_L2_PWRTRANS PWR_CTRL_REG(0x110)
-#define PWR_L2_PWRACTIVE PWR_CTRL_REG(0x118)
-#define PWR_TILER_PRESENT PWR_CTRL_REG(0x140)
-#define PWR_TILER_READY PWR_CTRL_REG(0x148)
-#define PWR_TILER_PWRTRANS PWR_CTRL_REG(0x150)
-#define PWR_TILER_PWRACTIVE PWR_CTRL_REG(0x158)
-#define PWR_SHADER_PRESENT PWR_CTRL_REG(0x200)
-#define PWR_SHADER_READY PWR_CTRL_REG(0x208)
-#define PWR_SHADER_PWRTRANS PWR_CTRL_REG(0x210)
-#define PWR_SHADER_PWRACTIVE PWR_CTRL_REG(0x218)
-#define PWR_BASE_PRESENT PWR_CTRL_REG(0x380)
-#define PWR_BASE_READY PWR_CTRL_REG(0x388)
-#define PWR_BASE_PWRTRANS PWR_CTRL_REG(0x390)
-#define PWR_BASE_PWRACTIVE PWR_CTRL_REG(0x398)
-#define PWR_STACK_PRESENT PWR_CTRL_REG(0x3c0)
-#define PWR_STACK_READY PWR_CTRL_REG(0x3c8)
-#define PWR_STACK_PWRTRANS PWR_CTRL_REG(0x3d0)
+#define PWR_L2_PRESENT 0x100
+#define PWR_L2_READY 0x108
+#define PWR_L2_PWRTRANS 0x110
+#define PWR_L2_PWRACTIVE 0x118
+#define PWR_TILER_PRESENT 0x140
+#define PWR_TILER_READY 0x148
+#define PWR_TILER_PWRTRANS 0x150
+#define PWR_TILER_PWRACTIVE 0x158
+#define PWR_SHADER_PRESENT 0x200
+#define PWR_SHADER_READY 0x208
+#define PWR_SHADER_PWRTRANS 0x210
+#define PWR_SHADER_PWRACTIVE 0x218
+#define PWR_BASE_PRESENT 0x380
+#define PWR_BASE_READY 0x388
+#define PWR_BASE_PWRTRANS 0x390
+#define PWR_BASE_PWRACTIVE 0x398
+#define PWR_STACK_PRESENT 0x3c0
+#define PWR_STACK_READY 0x3c8
+#define PWR_STACK_PWRTRANS 0x3d0
#endif /* __PANTHOR_PWR_REGS_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 6/8] drm/panthor: Use a local iomem base for PWR registers
2026-04-10 16:46 ` [PATCH 6/8] drm/panthor: Use a local iomem base for PWR registers Karunika Choo
@ 2026-04-10 18:12 ` Boris Brezillon
0 siblings, 0 replies; 17+ messages in thread
From: Boris Brezillon @ 2026-04-10 18:12 UTC (permalink / raw)
To: Karunika Choo
Cc: dri-devel, nd, Steven Price, Liviu Dudau, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
linux-kernel
On Fri, 10 Apr 2026 17:46:35 +0100
Karunika Choo <karunika.choo@arm.com> wrote:
> Add a PWR_CONTROL-local iomem pointer to struct panthor_pwr and switch
> power controller register accesses to that base.
>
> Keep interrupt register accesses on the IRQ-local iomem base and update
> the register definitions so the PWR block can be addressed relative to
> its local base. This removes the remaining dependence on the global
> device MMIO mapping for PWR register accesses.
>
> No functional change intended.
>
> Signed-off-by: Karunika Choo <karunika.choo@arm.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
> ---
> drivers/gpu/drm/panthor/panthor_pwr.c | 79 ++++++++++++++--------
> drivers/gpu/drm/panthor/panthor_pwr_regs.h | 50 +++++++-------
> 2 files changed, 74 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/panthor/panthor_pwr.c
> index 4f600a6688f9..f7fdbd15abf9 100644
> --- a/drivers/gpu/drm/panthor/panthor_pwr.c
> +++ b/drivers/gpu/drm/panthor/panthor_pwr.c
> @@ -40,6 +40,9 @@
> * struct panthor_pwr - PWR_CONTROL block management data.
> */
> struct panthor_pwr {
> + /** @iomem: CPU mapping of PWR_CONTROL iomem region */
> + void __iomem *iomem;
> +
> /** @irq: PWR irq. */
> struct panthor_irq irq;
>
> @@ -55,8 +58,10 @@ struct panthor_pwr {
>
> static void panthor_pwr_irq_handler(struct panthor_device *ptdev, u32 status)
> {
> + struct panthor_pwr *pwr = ptdev->pwr;
> +
> spin_lock(&ptdev->pwr->reqs_lock);
> - gpu_write(ptdev->iomem, PWR_INT_CLEAR, status);
> + gpu_write(pwr->irq.iomem, INT_CLEAR, status);
>
> if (unlikely(status & PWR_IRQ_COMMAND_NOT_ALLOWED))
> drm_err(&ptdev->base, "PWR_IRQ: COMMAND_NOT_ALLOWED");
> @@ -74,15 +79,19 @@ PANTHOR_IRQ_HANDLER(pwr, panthor_pwr_irq_handler);
>
> static void panthor_pwr_write_command(struct panthor_device *ptdev, u32 command, u64 args)
> {
> + struct panthor_pwr *pwr = ptdev->pwr;
> +
> if (args)
> - gpu_write64(ptdev->iomem, PWR_CMDARG, args);
> + gpu_write64(pwr->iomem, PWR_CMDARG, args);
>
> - gpu_write(ptdev->iomem, PWR_COMMAND, command);
> + gpu_write(pwr->iomem, PWR_COMMAND, command);
> }
>
> static bool reset_irq_raised(struct panthor_device *ptdev)
> {
> - return gpu_read(ptdev->iomem, PWR_INT_RAWSTAT) & PWR_IRQ_RESET_COMPLETED;
> + struct panthor_pwr *pwr = ptdev->pwr;
> +
> + return gpu_read(pwr->irq.iomem, INT_RAWSTAT) & PWR_IRQ_RESET_COMPLETED;
> }
>
> static bool reset_pending(struct panthor_device *ptdev)
> @@ -92,12 +101,14 @@ static bool reset_pending(struct panthor_device *ptdev)
>
> static int panthor_pwr_reset(struct panthor_device *ptdev, u32 reset_cmd)
> {
> + struct panthor_pwr *pwr = ptdev->pwr;
> +
> scoped_guard(spinlock_irqsave, &ptdev->pwr->reqs_lock) {
> if (reset_pending(ptdev)) {
> drm_WARN(&ptdev->base, 1, "Reset already pending");
> } else {
> ptdev->pwr->pending_reqs |= PWR_IRQ_RESET_COMPLETED;
> - gpu_write(ptdev->iomem, PWR_INT_CLEAR, PWR_IRQ_RESET_COMPLETED);
> + gpu_write(pwr->irq.iomem, INT_CLEAR, PWR_IRQ_RESET_COMPLETED);
> panthor_pwr_write_command(ptdev, reset_cmd, 0);
> }
> }
> @@ -182,11 +193,12 @@ static u8 get_domain_subdomain(struct panthor_device *ptdev, u32 domain)
> static int panthor_pwr_domain_wait_transition(struct panthor_device *ptdev, u32 domain,
> u32 timeout_us)
> {
> + struct panthor_pwr *pwr = ptdev->pwr;
> u32 pwrtrans_reg = get_domain_pwrtrans_reg(domain);
> u64 val;
> int ret = 0;
>
> - ret = gpu_read64_poll_timeout(ptdev->iomem, pwrtrans_reg, val, !(PWR_ALL_CORES_MASK & val), 100,
> + ret = gpu_read64_poll_timeout(pwr->iomem, pwrtrans_reg, val, !(PWR_ALL_CORES_MASK & val), 100,
> timeout_us);
> if (ret) {
> drm_err(&ptdev->base, "%s domain power in transition, pwrtrans(0x%llx)",
> @@ -199,22 +211,25 @@ static int panthor_pwr_domain_wait_transition(struct panthor_device *ptdev, u32
>
> static void panthor_pwr_debug_info_show(struct panthor_device *ptdev)
> {
> + struct panthor_pwr *pwr = ptdev->pwr;
> +
> drm_info(&ptdev->base, "GPU_FEATURES: 0x%016llx", ptdev->gpu_info.gpu_features);
> - drm_info(&ptdev->base, "PWR_STATUS: 0x%016llx", gpu_read64(ptdev->iomem, PWR_STATUS));
> - drm_info(&ptdev->base, "L2_PRESENT: 0x%016llx", gpu_read64(ptdev->iomem, PWR_L2_PRESENT));
> - drm_info(&ptdev->base, "L2_PWRTRANS: 0x%016llx", gpu_read64(ptdev->iomem, PWR_L2_PWRTRANS));
> - drm_info(&ptdev->base, "L2_READY: 0x%016llx", gpu_read64(ptdev->iomem, PWR_L2_READY));
> - drm_info(&ptdev->base, "TILER_PRESENT: 0x%016llx", gpu_read64(ptdev->iomem, PWR_TILER_PRESENT));
> - drm_info(&ptdev->base, "TILER_PWRTRANS: 0x%016llx", gpu_read64(ptdev->iomem, PWR_TILER_PWRTRANS));
> - drm_info(&ptdev->base, "TILER_READY: 0x%016llx", gpu_read64(ptdev->iomem, PWR_TILER_READY));
> - drm_info(&ptdev->base, "SHADER_PRESENT: 0x%016llx", gpu_read64(ptdev->iomem, PWR_SHADER_PRESENT));
> - drm_info(&ptdev->base, "SHADER_PWRTRANS: 0x%016llx", gpu_read64(ptdev->iomem, PWR_SHADER_PWRTRANS));
> - drm_info(&ptdev->base, "SHADER_READY: 0x%016llx", gpu_read64(ptdev->iomem, PWR_SHADER_READY));
> + drm_info(&ptdev->base, "PWR_STATUS: 0x%016llx", gpu_read64(pwr->iomem, PWR_STATUS));
> + drm_info(&ptdev->base, "L2_PRESENT: 0x%016llx", gpu_read64(pwr->iomem, PWR_L2_PRESENT));
> + drm_info(&ptdev->base, "L2_PWRTRANS: 0x%016llx", gpu_read64(pwr->iomem, PWR_L2_PWRTRANS));
> + drm_info(&ptdev->base, "L2_READY: 0x%016llx", gpu_read64(pwr->iomem, PWR_L2_READY));
> + drm_info(&ptdev->base, "TILER_PRESENT: 0x%016llx", gpu_read64(pwr->iomem, PWR_TILER_PRESENT));
> + drm_info(&ptdev->base, "TILER_PWRTRANS: 0x%016llx", gpu_read64(pwr->iomem, PWR_TILER_PWRTRANS));
> + drm_info(&ptdev->base, "TILER_READY: 0x%016llx", gpu_read64(pwr->iomem, PWR_TILER_READY));
> + drm_info(&ptdev->base, "SHADER_PRESENT: 0x%016llx", gpu_read64(pwr->iomem, PWR_SHADER_PRESENT));
> + drm_info(&ptdev->base, "SHADER_PWRTRANS: 0x%016llx", gpu_read64(pwr->iomem, PWR_SHADER_PWRTRANS));
> + drm_info(&ptdev->base, "SHADER_READY: 0x%016llx", gpu_read64(pwr->iomem, PWR_SHADER_READY));
> }
>
> static int panthor_pwr_domain_transition(struct panthor_device *ptdev, u32 cmd, u32 domain,
> u64 mask, u32 timeout_us)
> {
> + struct panthor_pwr *pwr = ptdev->pwr;
> u32 ready_reg = get_domain_ready_reg(domain);
> u32 pwr_cmd = PWR_COMMAND_DEF(cmd, domain, get_domain_subdomain(ptdev, domain));
> u64 expected_val = 0;
> @@ -241,12 +256,12 @@ static int panthor_pwr_domain_transition(struct panthor_device *ptdev, u32 cmd,
> return ret;
>
> /* domain already in target state, return early */
> - if ((gpu_read64(ptdev->iomem, ready_reg) & mask) == expected_val)
> + if ((gpu_read64(pwr->iomem, ready_reg) & mask) == expected_val)
> return 0;
>
> panthor_pwr_write_command(ptdev, pwr_cmd, mask);
>
> - ret = gpu_read64_poll_timeout(ptdev->iomem, ready_reg, val, (mask & val) == expected_val,
> + ret = gpu_read64_poll_timeout(pwr->iomem, ready_reg, val, (mask & val) == expected_val,
> 100, timeout_us);
> if (ret) {
> drm_err(&ptdev->base,
> @@ -279,8 +294,9 @@ static int panthor_pwr_domain_transition(struct panthor_device *ptdev, u32 cmd,
> */
> static int retract_domain(struct panthor_device *ptdev, u32 domain)
> {
> + struct panthor_pwr *pwr = ptdev->pwr;
> const u32 pwr_cmd = PWR_COMMAND_DEF(PWR_COMMAND_RETRACT, domain, 0);
> - const u64 pwr_status = gpu_read64(ptdev->iomem, PWR_STATUS);
> + const u64 pwr_status = gpu_read64(pwr->iomem, PWR_STATUS);
> const u64 delegated_mask = PWR_STATUS_DOMAIN_DELEGATED(domain);
> const u64 allow_mask = PWR_STATUS_DOMAIN_ALLOWED(domain);
> u64 val;
> @@ -289,7 +305,7 @@ static int retract_domain(struct panthor_device *ptdev, u32 domain)
> if (drm_WARN_ON(&ptdev->base, domain == PWR_COMMAND_DOMAIN_L2))
> return -EPERM;
>
> - ret = gpu_read64_poll_timeout(ptdev->iomem, PWR_STATUS, val,
> + ret = gpu_read64_poll_timeout(pwr->iomem, PWR_STATUS, val,
> !(PWR_STATUS_RETRACT_PENDING & val), 0,
> PWR_RETRACT_TIMEOUT_US);
> if (ret) {
> @@ -308,7 +324,7 @@ static int retract_domain(struct panthor_device *ptdev, u32 domain)
> * On successful retraction
> * allow-flag will be set with delegated-flag being cleared.
> */
> - ret = gpu_read64_poll_timeout(ptdev->iomem, PWR_STATUS, val,
> + ret = gpu_read64_poll_timeout(pwr->iomem, PWR_STATUS, val,
> ((delegated_mask | allow_mask) & val) == allow_mask, 10,
> PWR_TRANSITION_TIMEOUT_US);
> if (ret) {
> @@ -334,8 +350,9 @@ static int retract_domain(struct panthor_device *ptdev, u32 domain)
> */
> static int delegate_domain(struct panthor_device *ptdev, u32 domain)
> {
> + struct panthor_pwr *pwr = ptdev->pwr;
> const u32 pwr_cmd = PWR_COMMAND_DEF(PWR_COMMAND_DELEGATE, domain, 0);
> - const u64 pwr_status = gpu_read64(ptdev->iomem, PWR_STATUS);
> + const u64 pwr_status = gpu_read64(pwr->iomem, PWR_STATUS);
> const u64 allow_mask = PWR_STATUS_DOMAIN_ALLOWED(domain);
> const u64 delegated_mask = PWR_STATUS_DOMAIN_DELEGATED(domain);
> u64 val;
> @@ -364,7 +381,7 @@ static int delegate_domain(struct panthor_device *ptdev, u32 domain)
> * On successful delegation
> * allow-flag will be cleared with delegated-flag being set.
> */
> - ret = gpu_read64_poll_timeout(ptdev->iomem, PWR_STATUS, val,
> + ret = gpu_read64_poll_timeout(pwr->iomem, PWR_STATUS, val,
> ((delegated_mask | allow_mask) & val) == delegated_mask,
> 10, PWR_TRANSITION_TIMEOUT_US);
> if (ret) {
> @@ -412,7 +429,8 @@ static int panthor_pwr_delegate_domains(struct panthor_device *ptdev)
> */
> static int panthor_pwr_domain_force_off(struct panthor_device *ptdev, u32 domain)
> {
> - const u64 domain_ready = gpu_read64(ptdev->iomem, get_domain_ready_reg(domain));
> + struct panthor_pwr *pwr = ptdev->pwr;
> + const u64 domain_ready = gpu_read64(pwr->iomem, get_domain_ready_reg(domain));
> int ret;
>
> /* Domain already powered down, early exit. */
> @@ -456,6 +474,7 @@ int panthor_pwr_init(struct panthor_device *ptdev)
> if (!pwr)
> return -ENOMEM;
>
> + pwr->iomem = ptdev->iomem + GPU_CONTROL_BASE + PWR_CONTROL_BASE;
> spin_lock_init(&pwr->reqs_lock);
> init_waitqueue_head(&pwr->reqs_acked);
> ptdev->pwr = pwr;
> @@ -466,7 +485,7 @@ int panthor_pwr_init(struct panthor_device *ptdev)
>
> err = panthor_request_pwr_irq(ptdev, &pwr->irq, irq,
> PWR_INTERRUPTS_MASK,
> - GPU_CONTROL_BASE + PWR_CONTROL_BASE);
> + GPU_CONTROL_BASE + PWR_INT_BASE);
> if (err)
> return err;
>
> @@ -475,7 +494,9 @@ int panthor_pwr_init(struct panthor_device *ptdev)
>
> int panthor_pwr_reset_soft(struct panthor_device *ptdev)
> {
> - if (!(gpu_read64(ptdev->iomem, PWR_STATUS) & PWR_STATUS_ALLOW_SOFT_RESET)) {
> + struct panthor_pwr *pwr = ptdev->pwr;
> +
> + if (!(gpu_read64(pwr->iomem, PWR_STATUS) & PWR_STATUS_ALLOW_SOFT_RESET)) {
> drm_err(&ptdev->base, "RESET_SOFT not allowed");
> return -EOPNOTSUPP;
> }
> @@ -485,8 +506,9 @@ int panthor_pwr_reset_soft(struct panthor_device *ptdev)
>
> void panthor_pwr_l2_power_off(struct panthor_device *ptdev)
> {
> + struct panthor_pwr *pwr = ptdev->pwr;
> const u64 l2_allow_mask = PWR_STATUS_DOMAIN_ALLOWED(PWR_COMMAND_DOMAIN_L2);
> - const u64 pwr_status = gpu_read64(ptdev->iomem, PWR_STATUS);
> + const u64 pwr_status = gpu_read64(pwr->iomem, PWR_STATUS);
>
> /* Abort if L2 power off constraints are not satisfied */
> if (!(pwr_status & l2_allow_mask)) {
> @@ -512,7 +534,8 @@ void panthor_pwr_l2_power_off(struct panthor_device *ptdev)
>
> int panthor_pwr_l2_power_on(struct panthor_device *ptdev)
> {
> - const u32 pwr_status = gpu_read64(ptdev->iomem, PWR_STATUS);
> + struct panthor_pwr *pwr = ptdev->pwr;
> + const u32 pwr_status = gpu_read64(pwr->iomem, PWR_STATUS);
> const u32 l2_allow_mask = PWR_STATUS_DOMAIN_ALLOWED(PWR_COMMAND_DOMAIN_L2);
> int ret;
>
> diff --git a/drivers/gpu/drm/panthor/panthor_pwr_regs.h b/drivers/gpu/drm/panthor/panthor_pwr_regs.h
> index ad3e446971db..1fce05c3a96e 100644
> --- a/drivers/gpu/drm/panthor/panthor_pwr_regs.h
> +++ b/drivers/gpu/drm/panthor/panthor_pwr_regs.h
> @@ -5,12 +5,8 @@
> #define __PANTHOR_PWR_REGS_H__
>
> #define PWR_CONTROL_BASE 0x800
> -#define PWR_CTRL_REG(x) (PWR_CONTROL_BASE + (x))
>
> -#define PWR_INT_RAWSTAT PWR_CTRL_REG(0x0)
> -#define PWR_INT_CLEAR PWR_CTRL_REG(0x4)
> -#define PWR_INT_MASK PWR_CTRL_REG(0x8)
> -#define PWR_INT_STAT PWR_CTRL_REG(0xc)
> +#define PWR_INT_BASE 0x800
> #define PWR_IRQ_POWER_CHANGED_SINGLE BIT(0)
> #define PWR_IRQ_POWER_CHANGED_ALL BIT(1)
> #define PWR_IRQ_DELEGATION_CHANGED BIT(2)
> @@ -20,7 +16,7 @@
> #define PWR_IRQ_COMMAND_NOT_ALLOWED BIT(30)
> #define PWR_IRQ_COMMAND_INVALID BIT(31)
>
> -#define PWR_STATUS PWR_CTRL_REG(0x20)
> +#define PWR_STATUS 0x20
> #define PWR_STATUS_ALLOW_L2 BIT_U64(0)
> #define PWR_STATUS_ALLOW_TILER BIT_U64(1)
> #define PWR_STATUS_ALLOW_SHADER BIT_U64(8)
> @@ -41,7 +37,7 @@
> #define PWR_STATUS_RETRACT_PENDING BIT_U64(43)
> #define PWR_STATUS_INSPECT_PENDING BIT_U64(44)
>
> -#define PWR_COMMAND PWR_CTRL_REG(0x28)
> +#define PWR_COMMAND 0x28
> #define PWR_COMMAND_POWER_UP 0x10
> #define PWR_COMMAND_POWER_DOWN 0x11
> #define PWR_COMMAND_DELEGATE 0x20
> @@ -58,26 +54,26 @@
> #define PWR_COMMAND_DEF(cmd, domain, subdomain) \
> (((subdomain) << 16) | ((domain) << 8) | (cmd))
>
> -#define PWR_CMDARG PWR_CTRL_REG(0x30)
> +#define PWR_CMDARG 0x30
>
> -#define PWR_L2_PRESENT PWR_CTRL_REG(0x100)
> -#define PWR_L2_READY PWR_CTRL_REG(0x108)
> -#define PWR_L2_PWRTRANS PWR_CTRL_REG(0x110)
> -#define PWR_L2_PWRACTIVE PWR_CTRL_REG(0x118)
> -#define PWR_TILER_PRESENT PWR_CTRL_REG(0x140)
> -#define PWR_TILER_READY PWR_CTRL_REG(0x148)
> -#define PWR_TILER_PWRTRANS PWR_CTRL_REG(0x150)
> -#define PWR_TILER_PWRACTIVE PWR_CTRL_REG(0x158)
> -#define PWR_SHADER_PRESENT PWR_CTRL_REG(0x200)
> -#define PWR_SHADER_READY PWR_CTRL_REG(0x208)
> -#define PWR_SHADER_PWRTRANS PWR_CTRL_REG(0x210)
> -#define PWR_SHADER_PWRACTIVE PWR_CTRL_REG(0x218)
> -#define PWR_BASE_PRESENT PWR_CTRL_REG(0x380)
> -#define PWR_BASE_READY PWR_CTRL_REG(0x388)
> -#define PWR_BASE_PWRTRANS PWR_CTRL_REG(0x390)
> -#define PWR_BASE_PWRACTIVE PWR_CTRL_REG(0x398)
> -#define PWR_STACK_PRESENT PWR_CTRL_REG(0x3c0)
> -#define PWR_STACK_READY PWR_CTRL_REG(0x3c8)
> -#define PWR_STACK_PWRTRANS PWR_CTRL_REG(0x3d0)
> +#define PWR_L2_PRESENT 0x100
> +#define PWR_L2_READY 0x108
> +#define PWR_L2_PWRTRANS 0x110
> +#define PWR_L2_PWRACTIVE 0x118
> +#define PWR_TILER_PRESENT 0x140
> +#define PWR_TILER_READY 0x148
> +#define PWR_TILER_PWRTRANS 0x150
> +#define PWR_TILER_PWRACTIVE 0x158
> +#define PWR_SHADER_PRESENT 0x200
> +#define PWR_SHADER_READY 0x208
> +#define PWR_SHADER_PWRTRANS 0x210
> +#define PWR_SHADER_PWRACTIVE 0x218
> +#define PWR_BASE_PRESENT 0x380
> +#define PWR_BASE_READY 0x388
> +#define PWR_BASE_PWRTRANS 0x390
> +#define PWR_BASE_PWRACTIVE 0x398
> +#define PWR_STACK_PRESENT 0x3c0
> +#define PWR_STACK_READY 0x3c8
> +#define PWR_STACK_PWRTRANS 0x3d0
>
> #endif /* __PANTHOR_PWR_REGS_H__ */
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 7/8] drm/panthor: Use a local iomem base for firmware control registers
2026-04-10 16:46 [PATCH 0/8] drm/panthor: Localize register access by component Karunika Choo
` (5 preceding siblings ...)
2026-04-10 16:46 ` [PATCH 6/8] drm/panthor: Use a local iomem base for PWR registers Karunika Choo
@ 2026-04-10 16:46 ` Karunika Choo
2026-04-10 18:12 ` Boris Brezillon
2026-04-10 16:46 ` [PATCH 8/8] drm/panthor: Use a local iomem base for MMU AS registers Karunika Choo
7 siblings, 1 reply; 17+ messages in thread
From: Karunika Choo @ 2026-04-10 16:46 UTC (permalink / raw)
To: dri-devel
Cc: nd, Boris Brezillon, Steven Price, Liviu Dudau, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
linux-kernel
Add an MCU_CONTROL-local iomem pointer to struct panthor_fw and use it
for firmware control and status register accesses.
Job interrupt accesses continue to go through the IRQ-local base, while
doorbell writes stay on the device-wide mapping because they live
outside the MCU control window. This keeps firmware register accesses
scoped to the component that owns them.
No functional change intended.
Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
drivers/gpu/drm/panthor/panthor_fw.c | 20 +++++++++++++-------
drivers/gpu/drm/panthor/panthor_fw_regs.h | 11 ++++-------
2 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor/panthor_fw.c
index 20747f42759f..bf7c2baefb79 100644
--- a/drivers/gpu/drm/panthor/panthor_fw.c
+++ b/drivers/gpu/drm/panthor/panthor_fw.c
@@ -234,6 +234,9 @@ struct panthor_fw_iface {
* struct panthor_fw - Firmware management
*/
struct panthor_fw {
+ /** @iomem: CPU mapping of MCU_CONTROL iomem region */
+ void __iomem *iomem;
+
/** @vm: MCU VM. */
struct panthor_vm *vm;
@@ -1069,7 +1072,7 @@ static void panthor_job_irq_handler(struct panthor_device *ptdev, u32 status)
if (tracepoint_enabled(gpu_job_irq))
start = ktime_get_ns();
- gpu_write(ptdev->iomem, JOB_INT_CLEAR, status);
+ gpu_write(ptdev->fw->irq.iomem, INT_CLEAR, status);
if (!ptdev->fw->booted && (status & JOB_INT_GLOBAL_IF))
ptdev->fw->booted = true;
@@ -1092,18 +1095,19 @@ PANTHOR_IRQ_HANDLER(job, panthor_job_irq_handler);
static int panthor_fw_start(struct panthor_device *ptdev)
{
+ struct panthor_fw *fw = ptdev->fw;
bool timedout = false;
ptdev->fw->booted = false;
panthor_job_irq_enable_events(&ptdev->fw->irq, ~0);
panthor_job_irq_resume(&ptdev->fw->irq);
- gpu_write(ptdev->iomem, MCU_CONTROL, MCU_CONTROL_AUTO);
+ gpu_write(fw->iomem, MCU_CONTROL, MCU_CONTROL_AUTO);
if (!wait_event_timeout(ptdev->fw->req_waitqueue,
ptdev->fw->booted,
msecs_to_jiffies(1000))) {
if (!ptdev->fw->booted &&
- !(gpu_read(ptdev->iomem, JOB_INT_STAT) & JOB_INT_GLOBAL_IF))
+ !(gpu_read(fw->irq.iomem, INT_STAT) & JOB_INT_GLOBAL_IF))
timedout = true;
}
@@ -1114,7 +1118,7 @@ static int panthor_fw_start(struct panthor_device *ptdev)
[MCU_STATUS_HALT] = "halt",
[MCU_STATUS_FATAL] = "fatal",
};
- u32 status = gpu_read(ptdev->iomem, MCU_STATUS);
+ u32 status = gpu_read(fw->iomem, MCU_STATUS);
drm_err(&ptdev->base, "Failed to boot MCU (status=%s)",
status < ARRAY_SIZE(status_str) ? status_str[status] : "unknown");
@@ -1126,10 +1130,11 @@ static int panthor_fw_start(struct panthor_device *ptdev)
static void panthor_fw_stop(struct panthor_device *ptdev)
{
+ struct panthor_fw *fw = ptdev->fw;
u32 status;
- gpu_write(ptdev->iomem, MCU_CONTROL, MCU_CONTROL_DISABLE);
- if (gpu_read_poll_timeout(ptdev->iomem, MCU_STATUS, status,
+ gpu_write(fw->iomem, MCU_CONTROL, MCU_CONTROL_DISABLE);
+ if (gpu_read_poll_timeout(fw->iomem, MCU_STATUS, status,
status == MCU_STATUS_DISABLED, 10, 100000))
drm_err(&ptdev->base, "Failed to stop MCU");
}
@@ -1139,7 +1144,7 @@ static bool panthor_fw_mcu_halted(struct panthor_device *ptdev)
struct panthor_fw_global_iface *glb_iface = panthor_fw_get_glb_iface(ptdev);
bool halted;
- halted = gpu_read(ptdev->iomem, MCU_STATUS) == MCU_STATUS_HALT;
+ halted = gpu_read(ptdev->fw->iomem, MCU_STATUS) == MCU_STATUS_HALT;
if (panthor_fw_has_glb_state(ptdev))
halted &= (GLB_STATE_GET(glb_iface->output->ack) == GLB_STATE_HALT);
@@ -1461,6 +1466,7 @@ int panthor_fw_init(struct panthor_device *ptdev)
if (!fw)
return -ENOMEM;
+ fw->iomem = ptdev->iomem + MCU_CONTROL_BASE;
ptdev->fw = fw;
init_waitqueue_head(&fw->req_waitqueue);
INIT_LIST_HEAD(&fw->sections);
diff --git a/drivers/gpu/drm/panthor/panthor_fw_regs.h b/drivers/gpu/drm/panthor/panthor_fw_regs.h
index eeb41aff249b..b2e59cfc22b0 100644
--- a/drivers/gpu/drm/panthor/panthor_fw_regs.h
+++ b/drivers/gpu/drm/panthor/panthor_fw_regs.h
@@ -4,23 +4,20 @@
#ifndef __PANTHOR_FW_REGS_H__
#define __PANTHOR_FW_REGS_H__
-#define MCU_CONTROL 0x700
+#define MCU_CONTROL_BASE 0x700
+
+#define MCU_CONTROL 0x0
#define MCU_CONTROL_ENABLE 1
#define MCU_CONTROL_AUTO 2
#define MCU_CONTROL_DISABLE 0
-#define MCU_STATUS 0x704
+#define MCU_STATUS 0x4
#define MCU_STATUS_DISABLED 0
#define MCU_STATUS_ENABLED 1
#define MCU_STATUS_HALT 2
#define MCU_STATUS_FATAL 3
#define JOB_INT_BASE 0x1000
-
-#define JOB_INT_RAWSTAT 0x1000
-#define JOB_INT_CLEAR 0x1004
-#define JOB_INT_MASK 0x1008
-#define JOB_INT_STAT 0x100c
#define JOB_INT_GLOBAL_IF BIT(31)
#define JOB_INT_CSG_IF(x) BIT(x)
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 7/8] drm/panthor: Use a local iomem base for firmware control registers
2026-04-10 16:46 ` [PATCH 7/8] drm/panthor: Use a local iomem base for firmware control registers Karunika Choo
@ 2026-04-10 18:12 ` Boris Brezillon
0 siblings, 0 replies; 17+ messages in thread
From: Boris Brezillon @ 2026-04-10 18:12 UTC (permalink / raw)
To: Karunika Choo
Cc: dri-devel, nd, Steven Price, Liviu Dudau, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
linux-kernel
On Fri, 10 Apr 2026 17:46:36 +0100
Karunika Choo <karunika.choo@arm.com> wrote:
> Add an MCU_CONTROL-local iomem pointer to struct panthor_fw and use it
> for firmware control and status register accesses.
>
> Job interrupt accesses continue to go through the IRQ-local base, while
> doorbell writes stay on the device-wide mapping because they live
> outside the MCU control window. This keeps firmware register accesses
> scoped to the component that owns them.
>
> No functional change intended.
>
> Signed-off-by: Karunika Choo <karunika.choo@arm.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
> ---
> drivers/gpu/drm/panthor/panthor_fw.c | 20 +++++++++++++-------
> drivers/gpu/drm/panthor/panthor_fw_regs.h | 11 ++++-------
> 2 files changed, 17 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor/panthor_fw.c
> index 20747f42759f..bf7c2baefb79 100644
> --- a/drivers/gpu/drm/panthor/panthor_fw.c
> +++ b/drivers/gpu/drm/panthor/panthor_fw.c
> @@ -234,6 +234,9 @@ struct panthor_fw_iface {
> * struct panthor_fw - Firmware management
> */
> struct panthor_fw {
> + /** @iomem: CPU mapping of MCU_CONTROL iomem region */
> + void __iomem *iomem;
> +
> /** @vm: MCU VM. */
> struct panthor_vm *vm;
>
> @@ -1069,7 +1072,7 @@ static void panthor_job_irq_handler(struct panthor_device *ptdev, u32 status)
> if (tracepoint_enabled(gpu_job_irq))
> start = ktime_get_ns();
>
> - gpu_write(ptdev->iomem, JOB_INT_CLEAR, status);
> + gpu_write(ptdev->fw->irq.iomem, INT_CLEAR, status);
>
> if (!ptdev->fw->booted && (status & JOB_INT_GLOBAL_IF))
> ptdev->fw->booted = true;
> @@ -1092,18 +1095,19 @@ PANTHOR_IRQ_HANDLER(job, panthor_job_irq_handler);
>
> static int panthor_fw_start(struct panthor_device *ptdev)
> {
> + struct panthor_fw *fw = ptdev->fw;
> bool timedout = false;
>
> ptdev->fw->booted = false;
> panthor_job_irq_enable_events(&ptdev->fw->irq, ~0);
> panthor_job_irq_resume(&ptdev->fw->irq);
> - gpu_write(ptdev->iomem, MCU_CONTROL, MCU_CONTROL_AUTO);
> + gpu_write(fw->iomem, MCU_CONTROL, MCU_CONTROL_AUTO);
>
> if (!wait_event_timeout(ptdev->fw->req_waitqueue,
> ptdev->fw->booted,
> msecs_to_jiffies(1000))) {
> if (!ptdev->fw->booted &&
> - !(gpu_read(ptdev->iomem, JOB_INT_STAT) & JOB_INT_GLOBAL_IF))
> + !(gpu_read(fw->irq.iomem, INT_STAT) & JOB_INT_GLOBAL_IF))
> timedout = true;
> }
>
> @@ -1114,7 +1118,7 @@ static int panthor_fw_start(struct panthor_device *ptdev)
> [MCU_STATUS_HALT] = "halt",
> [MCU_STATUS_FATAL] = "fatal",
> };
> - u32 status = gpu_read(ptdev->iomem, MCU_STATUS);
> + u32 status = gpu_read(fw->iomem, MCU_STATUS);
>
> drm_err(&ptdev->base, "Failed to boot MCU (status=%s)",
> status < ARRAY_SIZE(status_str) ? status_str[status] : "unknown");
> @@ -1126,10 +1130,11 @@ static int panthor_fw_start(struct panthor_device *ptdev)
>
> static void panthor_fw_stop(struct panthor_device *ptdev)
> {
> + struct panthor_fw *fw = ptdev->fw;
> u32 status;
>
> - gpu_write(ptdev->iomem, MCU_CONTROL, MCU_CONTROL_DISABLE);
> - if (gpu_read_poll_timeout(ptdev->iomem, MCU_STATUS, status,
> + gpu_write(fw->iomem, MCU_CONTROL, MCU_CONTROL_DISABLE);
> + if (gpu_read_poll_timeout(fw->iomem, MCU_STATUS, status,
> status == MCU_STATUS_DISABLED, 10, 100000))
> drm_err(&ptdev->base, "Failed to stop MCU");
> }
> @@ -1139,7 +1144,7 @@ static bool panthor_fw_mcu_halted(struct panthor_device *ptdev)
> struct panthor_fw_global_iface *glb_iface = panthor_fw_get_glb_iface(ptdev);
> bool halted;
>
> - halted = gpu_read(ptdev->iomem, MCU_STATUS) == MCU_STATUS_HALT;
> + halted = gpu_read(ptdev->fw->iomem, MCU_STATUS) == MCU_STATUS_HALT;
>
> if (panthor_fw_has_glb_state(ptdev))
> halted &= (GLB_STATE_GET(glb_iface->output->ack) == GLB_STATE_HALT);
> @@ -1461,6 +1466,7 @@ int panthor_fw_init(struct panthor_device *ptdev)
> if (!fw)
> return -ENOMEM;
>
> + fw->iomem = ptdev->iomem + MCU_CONTROL_BASE;
> ptdev->fw = fw;
> init_waitqueue_head(&fw->req_waitqueue);
> INIT_LIST_HEAD(&fw->sections);
> diff --git a/drivers/gpu/drm/panthor/panthor_fw_regs.h b/drivers/gpu/drm/panthor/panthor_fw_regs.h
> index eeb41aff249b..b2e59cfc22b0 100644
> --- a/drivers/gpu/drm/panthor/panthor_fw_regs.h
> +++ b/drivers/gpu/drm/panthor/panthor_fw_regs.h
> @@ -4,23 +4,20 @@
> #ifndef __PANTHOR_FW_REGS_H__
> #define __PANTHOR_FW_REGS_H__
>
> -#define MCU_CONTROL 0x700
> +#define MCU_CONTROL_BASE 0x700
> +
> +#define MCU_CONTROL 0x0
> #define MCU_CONTROL_ENABLE 1
> #define MCU_CONTROL_AUTO 2
> #define MCU_CONTROL_DISABLE 0
>
> -#define MCU_STATUS 0x704
> +#define MCU_STATUS 0x4
> #define MCU_STATUS_DISABLED 0
> #define MCU_STATUS_ENABLED 1
> #define MCU_STATUS_HALT 2
> #define MCU_STATUS_FATAL 3
>
> #define JOB_INT_BASE 0x1000
> -
> -#define JOB_INT_RAWSTAT 0x1000
> -#define JOB_INT_CLEAR 0x1004
> -#define JOB_INT_MASK 0x1008
> -#define JOB_INT_STAT 0x100c
> #define JOB_INT_GLOBAL_IF BIT(31)
> #define JOB_INT_CSG_IF(x) BIT(x)
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 8/8] drm/panthor: Use a local iomem base for MMU AS registers
2026-04-10 16:46 [PATCH 0/8] drm/panthor: Localize register access by component Karunika Choo
` (6 preceding siblings ...)
2026-04-10 16:46 ` [PATCH 7/8] drm/panthor: Use a local iomem base for firmware control registers Karunika Choo
@ 2026-04-10 16:46 ` Karunika Choo
2026-04-10 18:13 ` Boris Brezillon
7 siblings, 1 reply; 17+ messages in thread
From: Karunika Choo @ 2026-04-10 16:46 UTC (permalink / raw)
To: dri-devel
Cc: nd, Boris Brezillon, Steven Price, Liviu Dudau, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
linux-kernel
Add an MMU_AS_CONTROL local iomem pointer to struct panthor_mmu and
switch AS register accesses to that base.
Interrupt accesses remain routed through the IRQ-local iomem base, while
the MMU register definitions are adjusted so AS registers are expressed
relative to the local MMU AS window. This completes the conversion away
from using the global device mapping for MMU AS register accesses.
No functional change intended.
Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
drivers/gpu/drm/panthor/panthor_mmu.c | 35 ++++++++++++++--------
drivers/gpu/drm/panthor/panthor_mmu_regs.h | 10 ++-----
2 files changed, 25 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c b/drivers/gpu/drm/panthor/panthor_mmu.c
index b8665e447d95..0767e148369d 100644
--- a/drivers/gpu/drm/panthor/panthor_mmu.c
+++ b/drivers/gpu/drm/panthor/panthor_mmu.c
@@ -55,6 +55,9 @@ struct panthor_as_slot {
* struct panthor_mmu - MMU related data
*/
struct panthor_mmu {
+ /** @iomem: CPU mapping of MMU_AS_CONTROL iomem region */
+ void __iomem *iomem;
+
/** @irq: The MMU irq. */
struct panthor_irq irq;
@@ -517,13 +520,14 @@ static void free_pt(void *cookie, void *data, size_t size)
static int wait_ready(struct panthor_device *ptdev, u32 as_nr)
{
+ struct panthor_mmu *mmu = ptdev->mmu;
int ret;
u32 val;
/* Wait for the MMU status to indicate there is no active command, in
* case one is pending.
*/
- ret = gpu_read_relaxed_poll_timeout_atomic(ptdev->iomem, AS_STATUS(as_nr), val,
+ ret = gpu_read_relaxed_poll_timeout_atomic(mmu->iomem, AS_STATUS(as_nr), val,
!(val & AS_STATUS_AS_ACTIVE), 10, 100000);
if (ret) {
@@ -541,7 +545,7 @@ static int as_send_cmd_and_wait(struct panthor_device *ptdev, u32 as_nr, u32 cmd
/* write AS_COMMAND when MMU is ready to accept another command */
status = wait_ready(ptdev, as_nr);
if (!status) {
- gpu_write(ptdev->iomem, AS_COMMAND(as_nr), cmd);
+ gpu_write(ptdev->mmu->iomem, AS_COMMAND(as_nr), cmd);
status = wait_ready(ptdev, as_nr);
}
@@ -589,12 +593,14 @@ PANTHOR_IRQ_HANDLER(mmu, panthor_mmu_irq_handler);
static int panthor_mmu_as_enable(struct panthor_device *ptdev, u32 as_nr,
u64 transtab, u64 transcfg, u64 memattr)
{
+ struct panthor_mmu *mmu = ptdev->mmu;
+
panthor_mmu_irq_enable_events(&ptdev->mmu->irq,
panthor_mmu_as_fault_mask(ptdev, as_nr));
- gpu_write64(ptdev->iomem, AS_TRANSTAB(as_nr), transtab);
- gpu_write64(ptdev->iomem, AS_MEMATTR(as_nr), memattr);
- gpu_write64(ptdev->iomem, AS_TRANSCFG(as_nr), transcfg);
+ gpu_write64(mmu->iomem, AS_TRANSTAB(as_nr), transtab);
+ gpu_write64(mmu->iomem, AS_MEMATTR(as_nr), memattr);
+ gpu_write64(mmu->iomem, AS_TRANSCFG(as_nr), transcfg);
return as_send_cmd_and_wait(ptdev, as_nr, AS_COMMAND_UPDATE);
}
@@ -602,6 +608,7 @@ static int panthor_mmu_as_enable(struct panthor_device *ptdev, u32 as_nr,
static int panthor_mmu_as_disable(struct panthor_device *ptdev, u32 as_nr,
bool recycle_slot)
{
+ struct panthor_mmu *mmu = ptdev->mmu;
struct panthor_vm *vm = ptdev->mmu->as.slots[as_nr].vm;
int ret;
@@ -629,9 +636,9 @@ static int panthor_mmu_as_disable(struct panthor_device *ptdev, u32 as_nr,
if (recycle_slot)
return 0;
- gpu_write64(ptdev->iomem, AS_TRANSTAB(as_nr), 0);
- gpu_write64(ptdev->iomem, AS_MEMATTR(as_nr), 0);
- gpu_write64(ptdev->iomem, AS_TRANSCFG(as_nr), AS_TRANSCFG_ADRMODE_UNMAPPED);
+ gpu_write64(mmu->iomem, AS_TRANSTAB(as_nr), 0);
+ gpu_write64(mmu->iomem, AS_MEMATTR(as_nr), 0);
+ gpu_write64(mmu->iomem, AS_TRANSCFG(as_nr), AS_TRANSCFG_ADRMODE_UNMAPPED);
return as_send_cmd_and_wait(ptdev, as_nr, AS_COMMAND_UPDATE);
}
@@ -784,7 +791,7 @@ int panthor_vm_active(struct panthor_vm *vm)
*/
fault_mask = panthor_mmu_as_fault_mask(ptdev, as);
if (ptdev->mmu->as.faulty_mask & fault_mask) {
- gpu_write(ptdev->iomem, MMU_INT_CLEAR, fault_mask);
+ gpu_write(ptdev->mmu->irq.iomem, INT_CLEAR, fault_mask);
ptdev->mmu->as.faulty_mask &= ~fault_mask;
}
@@ -1712,7 +1719,7 @@ static int panthor_vm_lock_region(struct panthor_vm *vm, u64 start, u64 size)
mutex_lock(&ptdev->mmu->as.slots_lock);
if (vm->as.id >= 0 && size) {
/* Lock the region that needs to be updated */
- gpu_write64(ptdev->iomem, AS_LOCKADDR(vm->as.id),
+ gpu_write64(ptdev->mmu->iomem, AS_LOCKADDR(vm->as.id),
pack_region_range(ptdev, &start, &size));
/* If the lock succeeded, update the locked_region info. */
@@ -1761,6 +1768,7 @@ static void panthor_vm_unlock_region(struct panthor_vm *vm)
static void panthor_mmu_irq_handler(struct panthor_device *ptdev, u32 status)
{
+ struct panthor_mmu *mmu = ptdev->mmu;
bool has_unhandled_faults = false;
status = panthor_mmu_fault_mask(ptdev, status);
@@ -1773,8 +1781,8 @@ static void panthor_mmu_irq_handler(struct panthor_device *ptdev, u32 status)
u32 access_type;
u32 source_id;
- fault_status = gpu_read(ptdev->iomem, AS_FAULTSTATUS(as));
- addr = gpu_read64(ptdev->iomem, AS_FAULTADDRESS(as));
+ fault_status = gpu_read(mmu->iomem, AS_FAULTSTATUS(as));
+ addr = gpu_read64(mmu->iomem, AS_FAULTADDRESS(as));
/* decode the fault status */
exception_type = fault_status & 0xFF;
@@ -1805,7 +1813,7 @@ static void panthor_mmu_irq_handler(struct panthor_device *ptdev, u32 status)
* Note that COMPLETED irqs are never cleared, but this is fine
* because they are always masked.
*/
- gpu_write(ptdev->iomem, MMU_INT_CLEAR, mask);
+ gpu_write(mmu->irq.iomem, INT_CLEAR, mask);
if (ptdev->mmu->as.slots[as].vm)
ptdev->mmu->as.slots[as].vm->unhandled_fault = true;
@@ -3222,6 +3230,7 @@ int panthor_mmu_init(struct panthor_device *ptdev)
if (ret)
return ret;
+ mmu->iomem = ptdev->iomem + MMU_AS_BASE;
ptdev->mmu = mmu;
irq = platform_get_irq_byname(to_platform_device(ptdev->base.dev), "mmu");
diff --git a/drivers/gpu/drm/panthor/panthor_mmu_regs.h b/drivers/gpu/drm/panthor/panthor_mmu_regs.h
index de460042651d..4e32ab931949 100644
--- a/drivers/gpu/drm/panthor/panthor_mmu_regs.h
+++ b/drivers/gpu/drm/panthor/panthor_mmu_regs.h
@@ -8,16 +8,12 @@
#define MMU_INT_BASE 0x2000
-#define MMU_INT_RAWSTAT 0x2000
-#define MMU_INT_CLEAR 0x2004
-#define MMU_INT_MASK 0x2008
-#define MMU_INT_STAT 0x200c
-
/* AS_COMMAND register commands */
-#define MMU_BASE 0x2400
+#define MMU_AS_BASE 0x2400
+
#define MMU_AS_SHIFT 6
-#define MMU_AS(as) (MMU_BASE + ((as) << MMU_AS_SHIFT))
+#define MMU_AS(as) ((as) << MMU_AS_SHIFT)
#define AS_TRANSTAB(as) (MMU_AS(as) + 0x0)
#define AS_MEMATTR(as) (MMU_AS(as) + 0x8)
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 8/8] drm/panthor: Use a local iomem base for MMU AS registers
2026-04-10 16:46 ` [PATCH 8/8] drm/panthor: Use a local iomem base for MMU AS registers Karunika Choo
@ 2026-04-10 18:13 ` Boris Brezillon
0 siblings, 0 replies; 17+ messages in thread
From: Boris Brezillon @ 2026-04-10 18:13 UTC (permalink / raw)
To: Karunika Choo
Cc: dri-devel, nd, Steven Price, Liviu Dudau, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
linux-kernel
On Fri, 10 Apr 2026 17:46:37 +0100
Karunika Choo <karunika.choo@arm.com> wrote:
> Add an MMU_AS_CONTROL local iomem pointer to struct panthor_mmu and
> switch AS register accesses to that base.
>
> Interrupt accesses remain routed through the IRQ-local iomem base, while
> the MMU register definitions are adjusted so AS registers are expressed
> relative to the local MMU AS window. This completes the conversion away
> from using the global device mapping for MMU AS register accesses.
>
> No functional change intended.
>
> Signed-off-by: Karunika Choo <karunika.choo@arm.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
> ---
> drivers/gpu/drm/panthor/panthor_mmu.c | 35 ++++++++++++++--------
> drivers/gpu/drm/panthor/panthor_mmu_regs.h | 10 ++-----
> 2 files changed, 25 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c b/drivers/gpu/drm/panthor/panthor_mmu.c
> index b8665e447d95..0767e148369d 100644
> --- a/drivers/gpu/drm/panthor/panthor_mmu.c
> +++ b/drivers/gpu/drm/panthor/panthor_mmu.c
> @@ -55,6 +55,9 @@ struct panthor_as_slot {
> * struct panthor_mmu - MMU related data
> */
> struct panthor_mmu {
> + /** @iomem: CPU mapping of MMU_AS_CONTROL iomem region */
> + void __iomem *iomem;
> +
> /** @irq: The MMU irq. */
> struct panthor_irq irq;
>
> @@ -517,13 +520,14 @@ static void free_pt(void *cookie, void *data, size_t size)
>
> static int wait_ready(struct panthor_device *ptdev, u32 as_nr)
> {
> + struct panthor_mmu *mmu = ptdev->mmu;
> int ret;
> u32 val;
>
> /* Wait for the MMU status to indicate there is no active command, in
> * case one is pending.
> */
> - ret = gpu_read_relaxed_poll_timeout_atomic(ptdev->iomem, AS_STATUS(as_nr), val,
> + ret = gpu_read_relaxed_poll_timeout_atomic(mmu->iomem, AS_STATUS(as_nr), val,
> !(val & AS_STATUS_AS_ACTIVE), 10, 100000);
>
> if (ret) {
> @@ -541,7 +545,7 @@ static int as_send_cmd_and_wait(struct panthor_device *ptdev, u32 as_nr, u32 cmd
> /* write AS_COMMAND when MMU is ready to accept another command */
> status = wait_ready(ptdev, as_nr);
> if (!status) {
> - gpu_write(ptdev->iomem, AS_COMMAND(as_nr), cmd);
> + gpu_write(ptdev->mmu->iomem, AS_COMMAND(as_nr), cmd);
> status = wait_ready(ptdev, as_nr);
> }
>
> @@ -589,12 +593,14 @@ PANTHOR_IRQ_HANDLER(mmu, panthor_mmu_irq_handler);
> static int panthor_mmu_as_enable(struct panthor_device *ptdev, u32 as_nr,
> u64 transtab, u64 transcfg, u64 memattr)
> {
> + struct panthor_mmu *mmu = ptdev->mmu;
> +
> panthor_mmu_irq_enable_events(&ptdev->mmu->irq,
> panthor_mmu_as_fault_mask(ptdev, as_nr));
>
> - gpu_write64(ptdev->iomem, AS_TRANSTAB(as_nr), transtab);
> - gpu_write64(ptdev->iomem, AS_MEMATTR(as_nr), memattr);
> - gpu_write64(ptdev->iomem, AS_TRANSCFG(as_nr), transcfg);
> + gpu_write64(mmu->iomem, AS_TRANSTAB(as_nr), transtab);
> + gpu_write64(mmu->iomem, AS_MEMATTR(as_nr), memattr);
> + gpu_write64(mmu->iomem, AS_TRANSCFG(as_nr), transcfg);
>
> return as_send_cmd_and_wait(ptdev, as_nr, AS_COMMAND_UPDATE);
> }
> @@ -602,6 +608,7 @@ static int panthor_mmu_as_enable(struct panthor_device *ptdev, u32 as_nr,
> static int panthor_mmu_as_disable(struct panthor_device *ptdev, u32 as_nr,
> bool recycle_slot)
> {
> + struct panthor_mmu *mmu = ptdev->mmu;
> struct panthor_vm *vm = ptdev->mmu->as.slots[as_nr].vm;
> int ret;
>
> @@ -629,9 +636,9 @@ static int panthor_mmu_as_disable(struct panthor_device *ptdev, u32 as_nr,
> if (recycle_slot)
> return 0;
>
> - gpu_write64(ptdev->iomem, AS_TRANSTAB(as_nr), 0);
> - gpu_write64(ptdev->iomem, AS_MEMATTR(as_nr), 0);
> - gpu_write64(ptdev->iomem, AS_TRANSCFG(as_nr), AS_TRANSCFG_ADRMODE_UNMAPPED);
> + gpu_write64(mmu->iomem, AS_TRANSTAB(as_nr), 0);
> + gpu_write64(mmu->iomem, AS_MEMATTR(as_nr), 0);
> + gpu_write64(mmu->iomem, AS_TRANSCFG(as_nr), AS_TRANSCFG_ADRMODE_UNMAPPED);
>
> return as_send_cmd_and_wait(ptdev, as_nr, AS_COMMAND_UPDATE);
> }
> @@ -784,7 +791,7 @@ int panthor_vm_active(struct panthor_vm *vm)
> */
> fault_mask = panthor_mmu_as_fault_mask(ptdev, as);
> if (ptdev->mmu->as.faulty_mask & fault_mask) {
> - gpu_write(ptdev->iomem, MMU_INT_CLEAR, fault_mask);
> + gpu_write(ptdev->mmu->irq.iomem, INT_CLEAR, fault_mask);
> ptdev->mmu->as.faulty_mask &= ~fault_mask;
> }
>
> @@ -1712,7 +1719,7 @@ static int panthor_vm_lock_region(struct panthor_vm *vm, u64 start, u64 size)
> mutex_lock(&ptdev->mmu->as.slots_lock);
> if (vm->as.id >= 0 && size) {
> /* Lock the region that needs to be updated */
> - gpu_write64(ptdev->iomem, AS_LOCKADDR(vm->as.id),
> + gpu_write64(ptdev->mmu->iomem, AS_LOCKADDR(vm->as.id),
> pack_region_range(ptdev, &start, &size));
>
> /* If the lock succeeded, update the locked_region info. */
> @@ -1761,6 +1768,7 @@ static void panthor_vm_unlock_region(struct panthor_vm *vm)
>
> static void panthor_mmu_irq_handler(struct panthor_device *ptdev, u32 status)
> {
> + struct panthor_mmu *mmu = ptdev->mmu;
> bool has_unhandled_faults = false;
>
> status = panthor_mmu_fault_mask(ptdev, status);
> @@ -1773,8 +1781,8 @@ static void panthor_mmu_irq_handler(struct panthor_device *ptdev, u32 status)
> u32 access_type;
> u32 source_id;
>
> - fault_status = gpu_read(ptdev->iomem, AS_FAULTSTATUS(as));
> - addr = gpu_read64(ptdev->iomem, AS_FAULTADDRESS(as));
> + fault_status = gpu_read(mmu->iomem, AS_FAULTSTATUS(as));
> + addr = gpu_read64(mmu->iomem, AS_FAULTADDRESS(as));
>
> /* decode the fault status */
> exception_type = fault_status & 0xFF;
> @@ -1805,7 +1813,7 @@ static void panthor_mmu_irq_handler(struct panthor_device *ptdev, u32 status)
> * Note that COMPLETED irqs are never cleared, but this is fine
> * because they are always masked.
> */
> - gpu_write(ptdev->iomem, MMU_INT_CLEAR, mask);
> + gpu_write(mmu->irq.iomem, INT_CLEAR, mask);
>
> if (ptdev->mmu->as.slots[as].vm)
> ptdev->mmu->as.slots[as].vm->unhandled_fault = true;
> @@ -3222,6 +3230,7 @@ int panthor_mmu_init(struct panthor_device *ptdev)
> if (ret)
> return ret;
>
> + mmu->iomem = ptdev->iomem + MMU_AS_BASE;
> ptdev->mmu = mmu;
>
> irq = platform_get_irq_byname(to_platform_device(ptdev->base.dev), "mmu");
> diff --git a/drivers/gpu/drm/panthor/panthor_mmu_regs.h b/drivers/gpu/drm/panthor/panthor_mmu_regs.h
> index de460042651d..4e32ab931949 100644
> --- a/drivers/gpu/drm/panthor/panthor_mmu_regs.h
> +++ b/drivers/gpu/drm/panthor/panthor_mmu_regs.h
> @@ -8,16 +8,12 @@
>
> #define MMU_INT_BASE 0x2000
>
> -#define MMU_INT_RAWSTAT 0x2000
> -#define MMU_INT_CLEAR 0x2004
> -#define MMU_INT_MASK 0x2008
> -#define MMU_INT_STAT 0x200c
> -
> /* AS_COMMAND register commands */
>
> -#define MMU_BASE 0x2400
> +#define MMU_AS_BASE 0x2400
> +
> #define MMU_AS_SHIFT 6
> -#define MMU_AS(as) (MMU_BASE + ((as) << MMU_AS_SHIFT))
> +#define MMU_AS(as) ((as) << MMU_AS_SHIFT)
>
> #define AS_TRANSTAB(as) (MMU_AS(as) + 0x0)
> #define AS_MEMATTR(as) (MMU_AS(as) + 0x8)
^ permalink raw reply [flat|nested] 17+ messages in thread