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([103.218.174.23]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35e41e1196asm2740502a91.1.2026.04.11.22.38.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Apr 2026 22:38:21 -0700 (PDT) From: Sudarshan Shetty To: andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org Cc: Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, marex@denx.de, valentin@compulab.co.il, luca.ceresoli@bootlin.com, philippe.schenker@toradex.com, alexander.stein@ew.tq-group.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Sudarshan Shetty Subject: [PATCH v3 0/1] drm: bridge: ti-sn65dsi83: Fix DSI mode flags for stable LVDS output Date: Sun, 12 Apr 2026 11:08:10 +0530 Message-Id: <20260412053811.662461-1-tessolveupstream@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi all, This patch refines dual-link LVDS support in the SN65DSI83/84 DSI-to-LVDS bridge driver. Recent upstream changes added support for dual-link LVDS timing adjustments and related fixes: - Halving horizontal timing parameters - Test pattern handling adjustments - DSI clock range correction However, during validation on our platform, LVDS output remained unstable for certain panels due to the DSI mode configuration. Specifically, the following flags were found to cause issues: - MIPI_DSI_MODE_VIDEO_NO_HFP - MIPI_DSI_MODE_VIDEO_NO_HBP These disable transmission of horizontal front porch (HFP) and back porch (HBP) timings over the DSI link. The SN65DSI bridge relies on complete horizontal timing information to reconstruct LVDS timings, and omitting these parameters results in incorrect or unstable output. Additionally: - MIPI_DSI_MODE_VIDEO_BURST While supported by the hardware, burst mode operation depends on continuous clocking from the DSI host. In practice, this may lead to instability depending on the host controller implementation, as the link may transition to LP mode between bursts. Removing these flags ensures that: - Full timing information is transmitted - The bridge can correctly reconstruct LVDS timings - Output remains stable across tested panels This patch updates the DSI mode configuration accordingly. This patch is based on recent SN65DSI83 dual-link LVDS fixes: - https://lore.kernel.org/lkml/20260309-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v2-1-e6aaa7e1d181@bootlin.com/ Changes in v3: - Rebased on top of latest upstream changes - Dropped previously proposed dual-link DT property and related handling as equivalent functionality is now available upstream - Refined DSI mode flag configuration to ensure stable LVDS output - Added detailed justification for removing NO_HFP/NO_HBP and BURST mode Changes in v2: - Introduced ti,dual-link-video-mode DT property - Added DT binding documentation for the new property - Update driver to read the DT property and apply dual-link configuration conditionally - Adjust DSI mode flags when dual-link video mode is enabled - Update commit messages Thanks, Anusha Sudarshan Shetty (1): drm: bridge: ti-sn65dsi83: Fix DSI mode flags for stable LVDS output drivers/gpu/drm/bridge/ti-sn65dsi83.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) -- 2.34.1