From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A535A3264CE for ; Thu, 16 Apr 2026 17:57:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776362241; cv=none; b=FKJxhdE/YE2FOxzhvgNTE7cK1LW9jYRKBg0OrDBzl8H+cWMgXzQwbF4ruUJg9t4h/nLrHi5MNM6YfDkfxEUAZpAFp38Rfn7pg9P9NX9gl/Azj/Nmo/pb4s4dBrI63xsBpnbgnTydzpYrHBRhrcYBR3cULyAhpt5lZiUX/fcM7b4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776362241; c=relaxed/simple; bh=l9/XGCFmUNwQod5vP59DMBBLRtrS7gHKb+3bXhugszg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FE53YqUDNgTvt4kkuXywjP8MNHXmz1T9SkgXS5SlUpAQWKZFimlmxzY1uMdCmS4Td2nOJwtXQ0t9d7uBgL/hToagXcuJggPkUfSQbos2ywG+UA/8+s7aCKCds9bzjICduj/zWnBGdBl5PwG+lneG1sT6IdyHQ1Sd3My3u2v04zE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=l84hoXEm; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="l84hoXEm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776362239; x=1807898239; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l9/XGCFmUNwQod5vP59DMBBLRtrS7gHKb+3bXhugszg=; b=l84hoXEmGCkJQ7+93aBBo+QSmn9ednXx7WVdnQPcZiodWW/39KuTWIzn gyrC6qP7dCx6Q6jqkPIRPz6L4F8TKznMcqGuSark87yzXiGfyjP6hL8d3 76KEjRDbMCccjiBCFBl9blhSzRuNF1bkpOJftROzHnJXBH4d6uUHq3wrY JMLGtWgpqCcfvKCJ5zsZJ+tN+gkLzpjJ25uyjUwhuYsX/bfTjAhv9jaC5 f5khEWs562TKC5Aa1owh0lhBhoQHi3cRQjNddf+xI0b4oeLZKtNwiJSO3 npn3UWYD7WtzjWn/vertRRR9cwsmLrw5cvireP+oIkzNioAUlCtfmNuka g==; X-CSE-ConnectionGUID: XdgzRZrLTUepPaHgnTc+nw== X-CSE-MsgGUID: 2tAOEFi7Rw6LX/xiE386aQ== X-IronPort-AV: E=McAfee;i="6800,10657,11761"; a="94778352" X-IronPort-AV: E=Sophos;i="6.23,181,1770624000"; d="scan'208";a="94778352" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:19 -0700 X-CSE-ConnectionGUID: kIiwc/EaSDmzZmXvO31fow== X-CSE-MsgGUID: QFePmp03S+iUz8tJOhaYog== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,181,1770624000"; d="scan'208";a="235784490" Received: from abityuts-desk.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.222]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:18 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/16] i3c: mipi-i3c-hci: Preserve RUN bit when aborting DMA ring Date: Thu, 16 Apr 2026 20:56:50 +0300 Message-ID: <20260416175704.41217-3-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260416175704.41217-1-adrian.hunter@intel.com> References: <20260416175704.41217-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: 8bit The MIPI I3C HCI specification does not require the DMA ring RUN bit (RUN_STOP) to be cleared when issuing an ABORT. Adjust the RING_CONTROL handling to set ABORT without clearing RUN_STOP, bringing the driver into alignment with the specification. According to the specification, that allows the DMA ring to continue to receive IBIs, although currently ABORT is only used in an error path so the change has very little effect in practice. Fixes: b795e68bf3073 ("i3c: mipi-i3c-hci: Correct RING_CTRL_ABORT handling in DMA dequeue") Signed-off-by: Adrian Hunter --- drivers/i3c/master/mipi-i3c-hci/dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mipi-i3c-hci/dma.c index e487ef52f6b4..4cd32e3afa7b 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -554,7 +554,7 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, if (ring_status & RING_STATUS_RUNNING) { /* stop the ring */ reinit_completion(&rh->op_done); - rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_ABORT); + rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); wait_for_completion_timeout(&rh->op_done, HZ); ring_status = rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { -- 2.51.0