Re: [PATCH 1/2] arm64: dts: imx8mq: Correct MIPI CSI clocks

Robby Cai
2026-04-30T07:56:34Z

On Fri, Apr 17, 2026 at 07:22:33AM -0400, Frank Li wrote:
> On Fri, Apr 17, 2026 at 07:01:59PM +0800, Robby Cai wrote:
> > CSI capture may intermittently fail due to mismatched clock rates. The
> > previous configuration violated the timing requirement stated in the
> > i.MX8MQ Reference Manual:
> >
> > "The frequency of clk must be exactly equal to or greater than the RX
> > byte clock coming from the RX DPHY."
> >
> > Update the clock configuration to ensure that the CSI core clock rate is
> > equal to or greater than the incoming DPHY byte clock.
>
> You reduce clock, how to make sure it >= ?

This is a mistake in the commit message. IMX8MQ_CLK_CSIX_PHY_REF refers to the
UI clock (clk_ui), not the RX DPHY byte clock. There is no direct >= relationship
with the CSI core clock other than the documented bandwidth requirement.

>
> > The updated clock
> > ratios are consistent with those used in NXP's downstream BSP.
>
> "downstream BSP" is not solidate reference for clock rate, it'd better
> refer to date sheet, dose datasheet require such frequecy
>
> Frank

I will revisit the clock assumptions in the next revision.

Regards,
Robby
> >
> > Fixes: bcadd5f66c2a ("arm64: dts: imx8mq: add mipi csi phy and csi bridge descriptions")
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Robby Cai <robby.cai@nxp.com>
> > --- …