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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43fe4e4d6casm4104912f8f.32.2026.04.17.06.17.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 06:17:37 -0700 (PDT) Date: Fri, 17 Apr 2026 14:17:36 +0100 From: David Laight To: Jinjie Ruan Cc: , , , , , , , , , , , Subject: Re: [PATCH v3 2/2] arch/riscv: Add bitrev.h file to support rev8 and brev8 Message-ID: <20260417141736.33a993e7@pumpkin> In-Reply-To: <20260417093102.3812978-3-ruanjinjie@huawei.com> References: <20260417093102.3812978-1-ruanjinjie@huawei.com> <20260417093102.3812978-3-ruanjinjie@huawei.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Fri, 17 Apr 2026 17:31:02 +0800 Jinjie Ruan wrote: > The RISC-V Bit-manipulation Extension for Cryptography (Zbkb) provides > the 'brev8' instruction, which reverses the bits within each byte. > Combined with the 'rev8' instruction (from Zbb or Zbkb), which reverses > the byte order of a register, we can efficiently implement 16-bit, > 32-bit, and (on RV64) 64-bit bit reversal. > > This is significantly faster than the default software table-lookup > implementation in lib/bitrev.c, as it replaces memory accesses and > multiple arithmetic operations with just two or three hardware > instructions. > > Select HAVE_ARCH_BITREVERSE and provide to utilize > these instructions when the Zbkb extension is available at runtime > via the alternatives mechanism. > > Link: https://docs.riscv.org/reference/isa/unpriv/b-st-ext.html > Signed-off-by: Jinjie Ruan > --- > arch/riscv/Kconfig | 1 + > arch/riscv/include/asm/bitrev.h | 55 +++++++++++++++++++++++++++++++++ > 2 files changed, 56 insertions(+) > create mode 100644 arch/riscv/include/asm/bitrev.h > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 90c531e6abf5..05f2b2166a83 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -128,6 +128,7 @@ config RISCV > select HAS_IOPORT if MMU > select HAVE_ALIGNED_STRUCT_PAGE > select HAVE_ARCH_AUDITSYSCALL > + select HAVE_ARCH_BITREVERSE if RISCV_ISA_ZBKB > select HAVE_ARCH_HUGE_VMALLOC if HAVE_ARCH_HUGE_VMAP > select HAVE_ARCH_HUGE_VMAP if MMU && 64BIT > select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL > diff --git a/arch/riscv/include/asm/bitrev.h b/arch/riscv/include/asm/bitrev.h > new file mode 100644 > index 000000000000..eef263cc6655 > --- /dev/null > +++ b/arch/riscv/include/asm/bitrev.h > @@ -0,0 +1,55 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __ASM_BITREV_H > +#define __ASM_BITREV_H > + > +#include > +#include > +#include > +#include > + > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > +{ > + unsigned long result = (unsigned long)x; Just: unsigned long result; > + > + if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBKB)) > + return generic___bitrev32(x); > + > + asm volatile( > + ".option push\n" > + ".option arch,+zbkb\n" > + "rev8 %0, %0\n" Replace the source with %1 > + "brev8 %0, %0\n" > + ".option pop" > + : "+r" (result) then: : "=r" (result) : "r" ((long)x) it is likely to save a register-register move > + ); > + > +#if __riscv_xlen == 64 > + return (u32)(result >> 32); > +#else > + return (u32)result; > +#endif There is no need to either cast, and the kernel style doesn't need them. (Filling code with casts that match the implicit conversions just makes it harder to find/check the ones that are absolutely necessary and actually change the behaviour.) You could just do: return result >> (__riscv_xlen - 32); > +} > + > +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) > +{ > + return __arch_bitrev32((u32)x) >> 16; Kill the cast. > +} > + > +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) > +{ > + unsigned long result = (unsigned long)x; > + > + if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBKB)) > + return generic___bitrev8(x); > + > + asm volatile( > + ".option push\n" > + ".option arch,+zbkb\n" > + "brev8 %0, %0\n" > + ".option pop" > + : "+r" (result) Use "=r" (result) : "r" ((long)x) again > + ); > + > + return (u8)result; Kill another cast. > +} > +#endif