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Peter Anvin" Subject: [PATCH RFC 3/6] x86/msr: Create a new minimal set of inter-CPU MSR access functions Date: Mon, 20 Apr 2026 11:16:31 +0200 Message-ID: <20260420091634.128787-4-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260420091634.128787-1-jgross@suse.com> References: <20260420091634.128787-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; FUZZY_RATELIMITED(0.00)[rspamd.com]; RCPT_COUNT_SEVEN(0.00)[8]; MIME_TRACE(0.00)[0:+]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; URIBL_BLOCKED(0.00)[suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-Spam-Score: -2.80 X-Spam-Level: Like for local MSR access functions create a set of inter-CPU MSR access functions using the "msr_" name space. For writing MSRs of other CPUs there is no need to have serializing and non-serializing variants. Base the new functions on the old ones for now. This can be changed when all callers have been changed to use the new functions only, in order to delete the old ones then. Signed-off-by: Juergen Gross --- arch/x86/include/asm/msr.h | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index cc21c8699e23..74e87b2b39fd 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -369,5 +369,37 @@ static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) #define wrmsrl(msr, val) wrmsrq(msr, val) #define rdmsrl_on_cpu(cpu, msr, q) rdmsrq_on_cpu(cpu, msr, q) +static inline int msr_read_on_cpu(unsigned int cpu, u32 msr, u64 *val) +{ + return rdmsrq_on_cpu(cpu, msr, val); +} + +static inline int msr_read_safe_on_cpu(unsigned int cpu, u32 msr, u64 *val) +{ + return rdmsrq_safe_on_cpu(cpu, msr, val); +} + +static inline int msr_write_on_cpu(unsigned int cpu, u32 msr, u64 val) +{ + return wrmsrq_on_cpu(cpu, msr, val); +} + +static inline int msr_write_safe_on_cpu(unsigned int cpu, u32 msr, u64 val) +{ + return wrmsrq_safe_on_cpu(cpu, msr, val); +} + +static inline void msr_read_on_cpus(const struct cpumask *cpus, u32 msr, + struct msr __percpu *msrs) +{ + rdmsr_on_cpus(cpus, msr, msrs); +} + +static inline void msr_write_on_cpus(const struct cpumask *cpus, u32 msr, + struct msr __percpu *msrs) +{ + wrmsr_on_cpus(cpus, msr, msrs); +} + #endif /* __ASSEMBLER__ */ #endif /* _ASM_X86_MSR_H */ -- 2.53.0