[PATCH v2 1/3] dt-bindings: clock: Add ESWIN eic7700 HSP clock and reset generator

dongxuyang
2026-04-20T09:40:27Z

Add bindings for the high-speed peripherals clock and reset generator
on the ESWIN EIC7700 HSP.

Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
.../bindings/clock/eswin,eic7700-hspcrg.yaml | 63 +++++++++++++++++++
MAINTAINERS | 5 +-
.../dt-bindings/clock/eswin,eic7700-hspcrg.h | 33 ++++++++++
.../dt-bindings/reset/eswin,eic7700-hspcrg.h | 21 +++++++
4 files changed, 120 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml
create mode 100644 include/dt-bindings/clock/eswin,eic7700-hspcrg.h
create mode 100644 include/dt-bindings/reset/eswin,eic7700-hspcrg.h

diff --git a/Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml b/Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml
new file mode 100644
index 000000000000..43df689ae647
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/eswin,eic7700-hspcrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ESWIN EIC7700 HSP Clock and Reset Generator
+
+maintainers:
+ - Xuyang Dong <dongxuyang@eswincomputing.com>
+
+description:
+ Clock and reset generator for the ESWIN EIC7700 HSP (high-speed peripherals).
+
+properties:
+ compatible:
+ const: eswin,eic7700-hspcrg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: HSP configuration top clock
+ - description: MMC top clock
+ - description: SATA top clock
+
+ clock-names:
+ items:
+ - const: cfg
+ - const: mmc
+ - const: sata
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/eswin,eic7700-hspcrg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/eswin,eic7700-hspcrg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@50440000 {
+ compatible = "eswin,eic7700-hspcrg";
+ reg = <0x50440000 0x2000>;
+ clocks = <&clock 171>, <&clock 254>, <&clock 187>;
+ clock-names = "cfg", "mmc", "sata";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index fe81fd3baedc..639fd11ebdd7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9573,9 +9573,10 @@ ESWIN EIC7700 CLOCK DRIVER
M: Yifeng Huang <huangyifeng@eswincomputing.com>
M: Xuyang Dong <dongxuyang@eswincomputing.com>
S: Maintained
-F: Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
+F: Documentation/devicetree/bindings/clock/eswin,eic7700*
F: drivers/clk/eswin/
-F: include/dt-bindings/clock/eswin,eic7700-clock.h
+F: include/dt-bindings/clock/eswin,eic7700*
+F: include/dt-bindings/reset/eswin,eic7700-hspcrg.h

ET131X NETWORK DRIVER
M: Mark Einon <mark.einon@gmail.com>
diff --git a/include/dt-bindings/clock/eswin,eic7700-hspcrg.h b/include/dt-bindings/clock/eswin,eic7700-hspcrg.h
new file mode 100644
index 000000000000..1d1ff15c1154
--- /dev/null
+++ b/include/dt-bindings/clock/eswin,eic7700-hspcrg.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * Device Tree binding constants for EIC7700 HSP clock controller.
+ *
+ * Authors: Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#ifndef _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_CLOCK_H_
+#define _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_CLOCK_H_
+
+#define EIC7700_HSP_CLK_FAC_CFG_DIV2 0
+#define EIC7700_HSP_CLK_FAC_CFG_DIV4 1
+#define EIC7700_HSP_CLK_FAC_MMC_DIV10 2
+#define EIC7700_HSP_CLK_MUX_EMMC_3MUX1 3
+#define EIC7700_HSP_CLK_MUX_SD0_3MUX1 4
+#define EIC7700_HSP_CLK_MUX_SD1_3MUX1 5
+#define EIC7700_HSP_CLK_MUX_EMMC_CQE_2MUX1 6
+#define EIC7700_HSP_CLK_MUX_SD0_CQE_2MUX1 7
+#define EIC7700_HSP_CLK_MUX_SD1_CQE_2MUX1 8
+#define EIC7700_HSP_CLK_GATE_MSHC0_TMR 9
+#define EIC7700_HSP_CLK_GATE_EMMC 10
+#define EIC7700_HSP_CLK_GATE_MSHC1_TMR 11
+#define EIC7700_HSP_CLK_GATE_SD0 12
+#define EIC7700_HSP_CLK_GATE_MSHC2_TMR 13
+#define EIC7700_HSP_CLK_GATE_SD1 14
+#define EIC7700_HSP_CLK_GATE_USB0 15
+#define EIC7700_HSP_CLK_GATE_USB1 16
+#define EIC7700_HSP_CLK_GATE_SATA 17
+
+#endif /* _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_CLOCK_H_ */
diff --git a/include/dt-bindings/reset/eswin,eic7700-hspcrg.h b/include/dt-bindings/reset/eswin,eic7700-hspcrg.h
new file mode 100644
index 000000000000..413fcd08c701
--- /dev/null
+++ b/include/dt-bindings/reset/eswin,eic7700-hspcrg.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * Device Tree binding constants for EIC7700 HSP reset controller.
+ *
+ * Authors: Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#ifndef _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_RESET_H_
+#define _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_RESET_H_
+
+#define EIC7700_HSP_RST_SATA_P0 0
+#define EIC7700_HSP_RST_SATA_PHY 1
+#define EIC7700_HSP_RST_USB0 2
+#define EIC7700_HSP_RST_USB1 3
+#define EIC7700_HSP_RST_USB0_PHY 4
+#define EIC7700_HSP_RST_USB1_PHY 5
+
+#endif /* _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_RESET_H_ */
--
2.43.0