From: Jason Gunthorpe <jgg@ziepe.ca>
To: Evangelos Petrongonas <epetron@amazon.de>
Cc: Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Joerg Roedel <joro@8bytes.org>,
Nicolin Chen <nicolinc@nvidia.com>,
Pranjal Shrivastava <praan@google.com>,
Lu Baolu <baolu.lu@linux.intel.com>,
linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
linux-kernel@vger.kernel.org, nh-open-source@amazon.com,
Zeev Zilberman <zeev@amazon.com>
Subject: Re: [PATCH] iommu/arm-smmu-v3: Allow disabling Stage 1 translation
Date: Mon, 20 Apr 2026 09:40:32 -0300 [thread overview]
Message-ID: <20260420124032.GO2577880@ziepe.ca> (raw)
In-Reply-To: <20260420123221.20801-1-epetron@amazon.de>
On Mon, Apr 20, 2026 at 12:32:01PM +0000, Evangelos Petrongonas wrote:
> When the hardware advertises both Stage 1 and Stage 2 translation, the
> driver prefers Stage 1 for DMA domain allocation and only falls back to
> Stage 2 if Stage 1 is not supported.
>
> Some configurations may want to force Stage 2 translation even when the
> hardware supports Stage 1.
Why? You really need to explain why for a patch like this.
If there really is some HW issue I think it is more appropriate to get
an IORT flag or IDR detection that the HW has a problem.
Jason
prev parent reply other threads:[~2026-04-20 12:40 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-20 12:32 [PATCH] iommu/arm-smmu-v3: Allow disabling Stage 1 translation Evangelos Petrongonas
2026-04-20 12:40 ` Jason Gunthorpe [this message]
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