From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC1211A6828; Tue, 21 Apr 2026 14:33:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776781980; cv=none; b=N+KMOoS14XrALwRj+0ek6b5ZQK+rAQhScjz3EQU0HX/2LunS9G72cTWqnzCLTa+gcfES/EmfV25gu1a7Gvm9ao3F8P14YxCVOkEx8h62g9GPW/xQPVbmngjrslEcuDuT96ElaB2VQnmRuVBlpFZT0cQVacHwF5vhvZmsEOFGivY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776781980; c=relaxed/simple; bh=q+/OSwNFmzUerRAiQV6WWVBVlt7S/h6k3KfMcobnMnY=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=abvB8wd1ZTUjHGt2TtZ8j0eumXIZQpsyTrUT8sutzSDm2mWPDFwBHfV9sSI6fiHUJGak6C43RVAtfgL2DkbA3CDjgjTuXIThWODNf3Yt4WsNtNO2+adbZ4fmP3kM49FameEB7stmkeJOJMWZgzh404yModMbuIJlFWtJYI954zk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=us9GcUqi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="us9GcUqi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A8F22C2BCB0; Tue, 21 Apr 2026 14:32:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776781980; bh=q+/OSwNFmzUerRAiQV6WWVBVlt7S/h6k3KfMcobnMnY=; h=From:To:Cc:Subject:Date:From; b=us9GcUqiGIax1QEAar9SHbhfPAR/IYayiHUwzBiTI8FaaNkxq0vzFhL7DkJrwFR5D VSA7l9OQfncs5P5nv63F0AecP2feLlsGlEqSIji9eUBqbVH4xyWJFrzj+IQBEOfwrp ncyKtXpnQSP/sn+a0KqzxUWhPSOJC5xPJAJS0jjwzFzX9v1/I/jX94HQ20zqGJOKbS 6xZgIXggRcqrmRsgkQwZPUHSzEEPl53JpAbG1TDqjGDrdCoZ6YgIa7A+z+XcF6syQ4 7Cc1oiSHGbLExNGSwMDw985px6pl2P/ZPZu2DSkWtNdnT42n7LXvyFkNTjGRXZiu9L MlXU8aFali59w== From: guoren@kernel.org To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Arnd Bergmann , Chen Wang , Inochi Amaoto , Leonardo Bras , "Guo Ren (Alibaba DAMO Academy)" , Raj Vishwanathan4 , Djordje Todorovic Cc: Alexandre Ghiti , Han Gao , Yao Zi , Xiaoguang Xing , Aleksandar Rikalo , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, sophgo@lists.linux.dev Subject: [PATCH V5] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup Date: Tue, 21 Apr 2026 10:31:40 -0400 Message-Id: <20260421143154.1590156-1-guoren@kernel.org> X-Mailer: git-send-email 2.40.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: "Guo Ren (Alibaba DAMO Academy)" The early version of XuanTie C910 core has a store merge buffer delay problem. The store merge buffer could improve the store queue performance by merging multi-store requests, but when there are not continued store requests, the prior single store request would be waiting in the store queue for a long time. That would cause significant problems for communication between multi-cores. This problem was found on sg2042 & th1520 platforms with the qspinlock lock torture test. So appending a fence w.o could immediately flush the store merge buffer and let other cores see the write result. This will apply the WRITE_ONCE errata to handle the non-standard behavior via appending a fence w.o instruction for WRITE_ONCE(). This problem is only observed on the sg2042 hardware platform by running the lock_torture test program for half an hour. The problem was not found in the user space application, because interrupt can break the livelock. Acked-by: Arnd Bergmann Reviewed-by: Alexandre Ghiti Reviewed-by: Leonardo Bras Reviewed-by: Inochi Amaoto Tested-by: Han Gao Tested-by: Yao Zi Cc: Chen Wang Cc: Xiaoguang Xing Cc: Paul Walmsley Signed-off-by: Guo Ren (Alibaba DAMO Academy) --- Changelog v5: - Add Acked-by: Arnd Bergmann for asm/generic - Add Reviewed-by: Inochi Amaoto - Rebase on v7.0 v4: https://lore.kernel.org/linux-riscv/20260412143116.1445893-1-guoren@kernel.org/ - Add Reviewed-by: Alexandre Ghiti (https://lore.kernel.org/linux-riscv/1cfdf6c1-a384-43ad-9588-284335d073f7@ghiti.fr/) - Add Tested-by: Yao Zi - Rebase on v7.0-rc7 v3: https://lore.kernel.org/linux-riscv/20260125063941.443777-1-guoren@kernel.org/ - Rebase on 6.19-rc6. - Remove errata_list_vendors patch which has been merged. - Add Tested-by tag. v2: https://lore.kernel.org/linux-riscv/20250713155321.2064856-1-guoren@kernel.org/ - Add new header file for errata_list_vendors. - Rebase newest kernel version. v1: https://lore.kernel.org/all/20241214143039.4139398-1-guoren@kernel.org/ --- arch/riscv/Kconfig.errata | 17 ++++++++++ arch/riscv/errata/thead/errata.c | 20 ++++++++++++ arch/riscv/include/asm/errata_list_vendors.h | 3 +- arch/riscv/include/asm/rwonce.h | 34 ++++++++++++++++++++ include/asm-generic/rwonce.h | 2 ++ 5 files changed, 75 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/rwonce.h diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 3c945d086c7d..4d3f13522da6 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -154,4 +154,21 @@ config ERRATA_THEAD_GHOSTWRITE If you don't know what to do here, say "Y". +config ERRATA_THEAD_WRITE_ONCE + bool "Apply T-Head WRITE_ONCE errata" + depends on ERRATA_THEAD + default y + help + The early version of T-Head C9xx cores of sg2042 & th1520 have a store + merge buffer delay problem. The store merge buffer could improve the + store queue performance by merging multi-store requests, but when there + are no continued store requests, the prior single store request would be + waiting in the store queue for a long time. That would cause signifi- + cant problems for communication between multi-cores. Appending a + fence w.o could immediately flush the store merge buffer and let other + cores see the write result. + + This will apply the WRITE_ONCE errata to handle the non-standard beh- + avior via appending a fence w.o instruction for WRITE_ONCE(). + endmenu # "CPU errata selection" diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index 0b942183f708..fbe46f2fa8fb 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -168,6 +168,23 @@ static bool errata_probe_ghostwrite(unsigned int stage, return true; } +static bool errata_probe_write_once(unsigned int stage, + unsigned long arch_id, unsigned long impid) +{ + if (!IS_ENABLED(CONFIG_ERRATA_THEAD_WRITE_ONCE)) + return false; + + /* target-c9xx cores report arch_id and impid as 0 */ + if (arch_id != 0 || impid != 0) + return false; + + if (stage == RISCV_ALTERNATIVES_BOOT || + stage == RISCV_ALTERNATIVES_MODULE) + return true; + + return false; +} + static u32 thead_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid) { @@ -183,6 +200,9 @@ static u32 thead_errata_probe(unsigned int stage, errata_probe_ghostwrite(stage, archid, impid); + if (errata_probe_write_once(stage, archid, impid)) + cpu_req_errata |= BIT(ERRATA_THEAD_WRITE_ONCE); + return cpu_req_errata; } diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/include/asm/errata_list_vendors.h index ec7eba373437..8fd7c36307e2 100644 --- a/arch/riscv/include/asm/errata_list_vendors.h +++ b/arch/riscv/include/asm/errata_list_vendors.h @@ -18,7 +18,8 @@ #define ERRATA_THEAD_MAE 0 #define ERRATA_THEAD_PMU 1 #define ERRATA_THEAD_GHOSTWRITE 2 -#define ERRATA_THEAD_NUMBER 3 +#define ERRATA_THEAD_WRITE_ONCE 3 +#define ERRATA_THEAD_NUMBER 4 #endif #ifdef CONFIG_ERRATA_MIPS diff --git a/arch/riscv/include/asm/rwonce.h b/arch/riscv/include/asm/rwonce.h new file mode 100644 index 000000000000..081793d4d772 --- /dev/null +++ b/arch/riscv/include/asm/rwonce.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __ASM_RWONCE_H +#define __ASM_RWONCE_H + +#include +#include +#include +#include + +#if defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) + +#define write_once_fence() \ +do { \ + asm volatile(ALTERNATIVE( \ + "nop", \ + "fence w, o", \ + THEAD_VENDOR_ID, \ + ERRATA_THEAD_WRITE_ONCE, \ + CONFIG_ERRATA_THEAD_WRITE_ONCE) \ + : : : "memory"); \ +} while (0) + +#define __WRITE_ONCE(x, val) \ +do { \ + *(volatile typeof(x) *)&(x) = (val); \ + write_once_fence(); \ +} while (0) + +#endif /* defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) */ + +#include + +#endif /* __ASM_RWONCE_H */ diff --git a/include/asm-generic/rwonce.h b/include/asm-generic/rwonce.h index 52b969c7cef9..4e2d941f15a1 100644 --- a/include/asm-generic/rwonce.h +++ b/include/asm-generic/rwonce.h @@ -50,10 +50,12 @@ __READ_ONCE(x); \ }) +#ifndef __WRITE_ONCE #define __WRITE_ONCE(x, val) \ do { \ *(volatile typeof(x) *)&(x) = (val); \ } while (0) +#endif #define WRITE_ONCE(x, val) \ do { \ -- 2.40.1