From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76D8F3A3E87 for ; Tue, 21 Apr 2026 17:54:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776794100; cv=none; b=Gw+0OZ0TM2IDJph7pZZnPg8hlZLRgIalBP0lr6Vu62NxqXui0PBXdJS/mArhOwEcy6PfAI9FvBcRYI1HYVXGUhCZeVQGGuq/rzi0BwPTsF1FrX66j7TFErAEMEUDtoba5c1Os2GTDcTADyvthd8A97IIsK9ifdL3pERiuxjUEbY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776794100; c=relaxed/simple; bh=UJnrAVRsnqnjwVIhz3L/WQih01nN54R0x5ENyDFj2iE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=C50plVTMOBNuLqMvB9Ffeq+tEmI+qbe25CR5nQOd5kYogd6pI87KH7DbdFp6pX/2r6rifXcz91FjxxK8q9REzlJuvPNqEEJq1FWtDOhEjgEj0h1J0+2Hw6NZaiSPPWjj5Cfb9Mkhdmj+FowayDfirXTV7AfDW4UEuYruMJh5Tuo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Fk6PLpIC; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Fk6PLpIC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776794097; x=1808330097; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UJnrAVRsnqnjwVIhz3L/WQih01nN54R0x5ENyDFj2iE=; b=Fk6PLpIC87V5hhpPt0pudwNttM3tCnoQR5IoUgJ3MltwKnky5FB8zphm Z4XK+xFcWKjVnuVR+5GVGibwjGQHJcJdTP4YZz8sEyjiT/dJMk+pSi+MB YFONOfX2JvdzoS+D/rR5XNTubWHTHakzCFIxDr9LGZYIwj9X1dsrGwv76 M828VmJTBtLKGaj6/gnwY4le03xrEw/vpt+cRxglZ18XYtBlv1yFCg6jh J7UOSV4fXmiWIaa+JbaPWQLoM9a+SAhly+pwHrRjdYdS5BGHTy4G80h4h KW+uPXmIuxcsYXzvEe4xw/vvFIsqbHlOcpZann13/DuhZ5fXluhtO2mf5 g==; X-CSE-ConnectionGUID: rE6nFo7MQlq4bxC+/lOGgg== X-CSE-MsgGUID: rNLgCHZjSRyX62h/AmcdGA== X-IronPort-AV: E=McAfee;i="6800,10657,11763"; a="77651364" X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="77651364" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:54:55 -0700 X-CSE-ConnectionGUID: aWyPJQApQ6KjbTAYUVVcpg== X-CSE-MsgGUID: FpWEjuEjQu+DJnbVTh9ohg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="227494888" Received: from hrotuna-mobl2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.242]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:54:53 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 04/16] i3c: mipi-i3c-hci: Wait for DMA ring restart to complete Date: Tue, 21 Apr 2026 20:54:23 +0300 Message-ID: <20260421175435.122094-5-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260421175435.122094-1-adrian.hunter@intel.com> References: <20260421175435.122094-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: 8bit Although hci_dma_dequeue_xfer() is serialized against itself via control_mutex, this does not guarantee that a DMA ring restart triggered by a previous invocation has fully completed. When the function is called again in rapid succession, the DMA ring may still be transitioning back to the running state, which may confound or disrupt further state changes. Address this by waiting for the DMA ring restart to complete before continuing. Signed-off-by: Adrian Hunter --- Changes in V2: None drivers/i3c/master/mipi-i3c-hci/dma.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mipi-i3c-hci/dma.c index 314635e6e190..28614fdbf558 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -617,6 +617,7 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, } /* restart the ring */ + reinit_completion(&rh->op_done); mipi_i3c_hci_resume(hci); rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE); rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_RUN_STOP); @@ -625,6 +626,8 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, spin_unlock_irq(&hci->lock); + wait_for_completion_timeout(&rh->op_done, HZ); + return did_unqueue; } -- 2.51.0