Re: [PATCH 10/13] clk: qcom: dispcc-sm8750: Add support to control MDP clocks using CESTA

Jagadeesh Kona
2026-04-28T17:22:01Z

On 4/23/2026 12:03 AM, Dmitry Baryshkov wrote:
> On Mon, Apr 20, 2026 at 09:59:03PM +0530, Jagadeesh Kona wrote:
>> Add support to control the DISPCC MDSS MDP RCG and the associated display
>> PLL0 using display CESTA hardware on SM8750 platform. If display CRM is
>> enabled, the clock ops of these clocks will be updated by the common code
>> before registration to use CRM specific clock ops, allowing these clocks
>> to be controlled using display CRM (CESTA Resource Manager) hardware.
>>
>> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
>> Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
>> ---
>> drivers/clk/qcom/dispcc-sm8750.c | 89 +++++++++++++++++++++++++---------------
>> 1 file changed, 56 insertions(+), 33 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/dispcc-sm8750.c b/drivers/clk/qcom/dispcc-sm8750.c
>> index ca09da111a50e811481fd862b54d454de024d1c9..328e43b52192702dbbfd1ed65737520acdd4a649 100644
>> --- a/drivers/clk/qcom/dispcc-sm8750.c
>> +++ b/drivers/clk/qcom/dispcc-sm8750.c
>> @@ -71,6 +71,16 @@ enum {
>> P_SLEEP_CLK,
>> };
>>
>> +static struct clk_crm disp_crm = {
>> + .max_perf_ol = 10,
>> + .regs = {
>> + .reg_cfg_rcgr_lut_base = 0xd8,
>> + .reg_l_val_lut_base = 0xdc,
>> + .vcd_offset = 0x268,
>> + .lut_level_offset = 0x28,
>
> Seeing this configuration makes me even more sure. There is no separate
> CRM or disp-crm. The CRM resources should be consumed by dispcc.
>

The CRM can be used by interconnect drivers also for BW voting via CESTA.
Hence it cannot be consumed by dispcc alone.

>> + },
>> +};
>> +
>> static const struct pll_vco pongo_elu_vco[] = {
>> { 38400000, 38400000, 0 },
>> };
>> @@ -89,21 +99,22 @@ static struct alpha_pll_config disp_cc_pll0_config = {
>> .user_ctl_hi_val = 0x00000002,
>> };
>>
>> +static struct clk_init_data disp_cc_pll0_init = {
>> + .name = "disp_cc_pll0",
>> + .parent_data = &(const struct clk_parent_data) {
>> + .index = DT_BI_TCXO,
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_GET_RATE_NOCACHE,
>
> Why? It wasn't there beforehand.
>

The PLL rate can be changed by CESTA outside of the PLL callbacks, when a perf level request
is sent via CRM API in RCG's prepare()/set_rate() callbacks. Having this flag ensures that the
PLL rate is recalculated from hardware every time when users query the PLL's clk_rate node,
providing the correct PLL rate configured by CESTA.

Thanks,
Jagadeesh