From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31EE83E92A1 for ; Thu, 23 Apr 2026 10:19:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776939582; cv=none; b=ekP84iGWj7BdnTiUCoGteZFBqk/REaAkkALsN7gWxta1oltny9yTovqHDEmmxoVrRWFTYxBmmlE5WzMZ4BzBKheyZWdbXKaZ9l6I5k5/M97znpRAGeHnPw3ZtZDNqF3oBCqgeYE2FxQfHAULbHCKcYTll3hspqOCZG1d+9osRJ4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776939582; c=relaxed/simple; bh=cHcm5apaxrM/bdKTAfTPAHbQ+naHeG9FAEo9kwK5j3o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Zb9eBqbtH8QrL+Th/yHapiGgiRYKYimBXWEFfDOtTjfU8xNAswI3SRpwaX2k0JbN0EyUCaieA0FmgxEOZj5ey5Vpo4sNVj7yT67utxGHrQYrrYPEySYt+/w/hvxYDV1GYAK2QZ1jj65in5cOe2iF3gT4bvw1sKjE8OdsNBwWxzo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kqQzmTpv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kqQzmTpv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 71D88C2BCB2; Thu, 23 Apr 2026 10:19:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776939581; bh=cHcm5apaxrM/bdKTAfTPAHbQ+naHeG9FAEo9kwK5j3o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=kqQzmTpvZ0Ll4qzqnuGsafpBBS+JeQ7JvBzZsL8aAR/e5myf1yHfS6pcfnNOVelDT sgBsc12Ng+TTaPlfTm2MeGP5qgiqaseTzJH1eGnLjcMQEsaxd0IlGzaa1GASs4r6LH Y+KFTQT87agVo03/jdDVxqpnHUsRgUW14+QSq/C4U6FkhN8LO/ibl3gO5ykeqQOY21 8JjYKCnwjdb/eHsGy8ZMZ2i3QoeKrDQEioM2gaFrJXvLNyrC+sYi9NVXX3//Lgf2pV 0QpncX8DLIRl8SC1gai1k845a1krymEXLi3dtA9FDYUHHhNvgwUUyHM+xekUFS5TAN 8eouX03k2YnWw== From: Maxime Ripard Date: Thu, 23 Apr 2026 12:18:38 +0200 Subject: [PATCH v2 25/28] drm/tidss: dispc: Improve mode checking logs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260423-drm-state-readout-v2-25-8549f87cb978@kernel.org> References: <20260423-drm-state-readout-v2-0-8549f87cb978@kernel.org> In-Reply-To: <20260423-drm-state-readout-v2-0-8549f87cb978@kernel.org> To: Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Jyri Sarha , Tomi Valkeinen Cc: Devarsh Thakkar , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4777; i=mripard@kernel.org; h=from:subject:message-id; bh=cHcm5apaxrM/bdKTAfTPAHbQ+naHeG9FAEo9kwK5j3o=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDJkvP34qOLXw0myGnTyWMRyzK1/xM9UcXe47SXyX0DO/l rP+ZZ48HVNZGIQ5GWTFFFmeyISdXt6+uMrBfuUPmDmsTCBDGLg4BWAiVjmMDScNlhlGmjRe69p3 SsF+gcLnCQe/M8/YOpd993RZ3jAfY6HWZysPxK17MDuSw0mOiSk1nrHO4OClp4e590/tMVp8T+7 EXpsic03vizm33De+FbNi2qD/+FJd+vYFG+fJBucZnWaPlmoGAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The dispc_vp_mode_valid() function checks whether a mode can be handled by the display controller. There's a whole bunch of criteria, and it's not clear when a rejection happens why it did. Add logs on each rejection criterion to make it clearer. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 45 +++++++++++++++++++++++++++++-------- 1 file changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index 34bafe951924..c24c06cae10b 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -1317,10 +1317,12 @@ unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate) } static int check_pixel_clock(struct dispc_device *dispc, u32 hw_videoport, unsigned long clock) { + struct tidss_device *tidss = dispc->tidss; + struct drm_device *dev = &tidss->ddev; unsigned long round_clock; /* * For VP's with external clocking, clock operations must be * delegated to respective driver, so we skip the check here. @@ -1331,51 +1333,65 @@ static int check_pixel_clock(struct dispc_device *dispc, u32 hw_videoport, round_clock = clk_round_rate(dispc->vp_clk[hw_videoport], clock); /* * To keep the check consistent with dispc_vp_set_clk_rate(), we * use the same 5% check here. */ - if (dispc_pclk_diff(clock, round_clock) > 5) + if (dispc_pclk_diff(clock, round_clock) > 5) { + drm_dbg(dev, "Mode pixel clock below hardware minimum pixel clock."); return -EINVAL; + } return 0; } enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc, u32 hw_videoport, const struct drm_display_mode *mode) { + struct tidss_device *tidss = dispc->tidss; + struct drm_device *dev = &tidss->ddev; u32 hsw, hfp, hbp, vsw, vfp, vbp; enum dispc_vp_bus_type bus_type; bus_type = dispc->feat->vp_bus_type[hw_videoport]; - if (WARN_ON(bus_type == DISPC_VP_TIED_OFF)) + if (WARN_ON(bus_type == DISPC_VP_TIED_OFF)) { + drm_dbg(dev, "Invalid bus type."); return MODE_BAD; + } - if (mode->hdisplay > 4096) + if (mode->hdisplay > 4096) { + drm_dbg(dev, "Number of active horizontal pixels above hardware limits."); return MODE_BAD; + } - if (mode->vdisplay > 4096) + if (mode->vdisplay > 4096) { + drm_dbg(dev, "Number of active vertical lines above hardware limits."); return MODE_BAD; + } if (check_pixel_clock(dispc, hw_videoport, mode->clock * 1000)) return MODE_CLOCK_RANGE; /* TODO: add interlace support */ - if (mode->flags & DRM_MODE_FLAG_INTERLACE) + if (mode->flags & DRM_MODE_FLAG_INTERLACE) { + drm_dbg(dev, "Interlace modes not supported."); return MODE_NO_INTERLACE; + } /* * Enforce the output width is divisible by 2. Actually this * is only needed in following cases: * - YUV output selected (BT656, BT1120) * - Dithering enabled * - TDM with TDMCycleFormat == 3 * But for simplicity we enforce that always. */ - if ((mode->hdisplay % 2) != 0) + if ((mode->hdisplay % 2) != 0) { + drm_dbg(dev, "Number of active horizontal pixels must be even."); return MODE_BAD_HVALUE; + } hfp = mode->hsync_start - mode->hdisplay; hsw = mode->hsync_end - mode->hsync_start; hbp = mode->htotal - mode->hsync_end; @@ -1383,29 +1399,40 @@ enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc, vsw = mode->vsync_end - mode->vsync_start; vbp = mode->vtotal - mode->vsync_end; if (hsw < 1 || hsw > 256 || hfp < 1 || hfp > 4096 || - hbp < 1 || hbp > 4096) + hbp < 1 || hbp > 4096) { + drm_dbg(dev, + "Horizontal blanking or sync outside of hardware limits (fp: %u, sw: %u, bp: %u).", + hfp, hsw, hbp); return MODE_BAD_HVALUE; + } if (vsw < 1 || vsw > 256 || - vfp > 4095 || vbp > 4095) + vfp > 4095 || vbp > 4095) { + drm_dbg(dev, + "Vertical blanking or sync outside of hardware limits (fp: %u, sw: %u, bp: %u).", + vfp, vsw, vbp); return MODE_BAD_VVALUE; + } if (dispc->memory_bandwidth_limit) { const unsigned int bpp = 4; u64 bandwidth; bandwidth = 1000 * mode->clock; bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp; bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal); - if (dispc->memory_bandwidth_limit < bandwidth) + if (dispc->memory_bandwidth_limit < bandwidth) { + drm_dbg(dev, "Required memory bandwidth outside of hardware limits."); return MODE_BAD; + } } + drm_dbg(dev, "Mode is valid."); return MODE_OK; } int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport) { -- 2.53.0