[PATCH V1 1/3] ACPICA: IORT: Add Root Complex PASID Flags field

Vidya Sagar
2026-04-23T19:15:10Z

The IORT spec, Issue E.c (ARM DEN 0049E.c, January 2022), bumps the
Root Complex Node to revision 4 and adds two PASID descriptors:

- PASID Capabilities at byte offset 33 (2 bytes), bits[4:0] of which
report the Max PASID Width supported by the Root Complex.
- Flags at byte offset 36 (4 bytes), bit 0 of which reports whether
the Root Complex itself supports PASID. This is distinct from the
existing ATS Attribute bit 2 (at offset 24) that only reports
whether the RC forwards PASID information on translated
transactions.

The ACPICA struct in include/acpi/actbl2.h was updated for the E.c
PASID Capabilities descriptor (offset 33) but stops short with a
trailing 'u8 reserved[]' flexible array, so the new Flags field at
offset 36 is unreachable and the existing ACPI_IORT_PASID_*
definitions have no consumer.

Replace the trailing flexible array with a fixed 'u8 reserved[1]'
followed by 'u32 flags' so the struct fully covers RC node revision 4,
and add the ACPI_IORT_RC_PASID_SUPPORTED mask for bit 0 of the new
field. With #pragma pack(1) in effect for actbl2.h, this lands the new
field at the spec-mandated absolute offset 36.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
include/acpi/actbl2.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
index 5c0b55e7b3e4..5a4450e66358 100644
--- a/include/acpi/actbl2.h
+++ b/include/acpi/actbl2.h
@@ -748,7 +748,8 @@ struct acpi_iort_root_complex {
u32 pci_segment_number;
u8 memory_address_limit; /* Memory address size limit */
u16 pasid_capabilities; /* PASID Capabilities */
- u8 reserved[]; /* Reserved, must be zero */
+ u8 reserved[1]; /* Reserved, must be zero */
+ u32 flags; /* Flags (IORT E.c, RC node revision >= 4) */
};

/* Masks for ats_attribute field above */
@@ -760,6 +761,9 @@ struct acpi_iort_root_complex {
/* Masks for pasid_capabilities field above */
#define ACPI_IORT_PASID_MAX_WIDTH (0x1F) /* Bits 0-4 */

+/* Masks for flags field above */
+#define ACPI_IORT_RC_PASID_SUPPORTED (1) /* The root complex PASID support */
+
struct acpi_iort_smmu {
u64 base_address; /* SMMU base address */
u64 span; /* Length of memory range */
--
2.25.1