[PATCH v3 6/6] arm64: tegra: Add pinctrl nodes for Tegra264

pshete
2026-04-27T13:44:00Z

Add the three pin controller (MAIN, UPHY, AON) device-tree nodes found on
Tegra264.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
---
Changes in v3:
- Wrap commit message to 75 chars per line (v2 was too short).
Changes in v2:
- This patch is added as part of v2.
---
arch/arm64/boot/dts/nvidia/tegra264.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index 06d8357bdf52..dc7793088d2e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -3380,6 +3380,11 @@ i2c3: i2c@c610000 {
status = "disabled";
};

+ pinmux_aon: pinmux@c7a2000 {
+ compatible = "nvidia,tegra264-pinmux-aon";
+ reg = <0x0 0x0c7a2000 0x0 0x2000>;
+ };
+
pmc: pmc@c800000 {
compatible = "nvidia,tegra264-pmc";
reg = <0x0 0x0c800000 0x0 0x100000>,
@@ -3586,6 +3591,11 @@ pci@c000000 {
status = "disabled";
};

+ pinmux_main: pinmux@c281000 {
+ compatible = "nvidia,tegra264-pinmux-main";
+ reg = <0x00 0x0c281000 0x0 0xc000>;
+ };
+
i2c14: i2c@c410000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x00 0x0c410000 0x0 0x10000>;
@@ -3862,6 +3872,11 @@ bus@a800000000 {
<0x00 0x20000000 0x00 0x20000000 0x00 0x60000000>, /* non-prefetchable memory (32-bit, 1536 GiB) */
<0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */

+ pinmux_uphy: pinmux@82e0000 {
+ compatible = "nvidia,tegra264-pinmux-uphy";
+ reg = <0x00 0x082e0000 0x0 0x4000>;
+ };
+
gpio_uphy: gpio@8300000 {
compatible = "nvidia,tegra264-gpio-uphy";
reg = <0x00 0x08300000 0x0 0x2000>,
--
2.43.0