From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C1F623D34B2 for ; Mon, 27 Apr 2026 14:02:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777298531; cv=none; b=EHkqqxRaD7TNw/UoNjIpJk1NowBkSSqNfB2ArYUJLjk4GouCsKaBZsGN3QcR3zmzWQxcFOVws6B9jd98Syio/QUah9+V7mfANrh+BjNVhGCkGSAQR2IynqpsEC6rCPLKdPmYB2AjjBPyKTX4AAiQJo2PzK7ok5Q2hHdQ29NDgGM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777298531; c=relaxed/simple; bh=dD4PWRYpo7EHK+a11lx5u+lWacH6ZMzCfigDfNpRHCU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZshEA0MWk2mY9jNMH+NyHY2Q/ZiXNxaC1X26gGc3kYs+dJyrlfb0DAcZLRL1TQpKklBYlYpqDneBPJnuqMnNgExxR7+xd31nLBQGVtYm0lMJ3wn0F+c8+46lc4RTUNKHC1G/pXelfw0lvgTwNI4Zs4SwtLrD5yOLp4xh3HBALZg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=PQrIg21H; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="PQrIg21H" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 93C9C1684; Mon, 27 Apr 2026 07:02:03 -0700 (PDT) Received: from devkitleo.cambridge.arm.com (devkitleo.cambridge.arm.com [10.1.196.90]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 62DC43F763; Mon, 27 Apr 2026 07:02:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1777298529; bh=dD4PWRYpo7EHK+a11lx5u+lWacH6ZMzCfigDfNpRHCU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PQrIg21Ha1aurXj/LExfbLHCS3IMKDho+xnBA8PjVaaqDApBKl8Tc444WcIND0x6W DbxWdi1ITnHpBNA92vXAv0vKiTv9fY8/B9/hHhYmYPtzU0kwb65dz3WBIgz9IfqSNo KvaNPkF8QX79D3TrJ4u+W9073c0YUGLeXE0+RHi0= From: Leonardo Bras To: mark.rutland@arm.com Cc: catalin.marinas@arm.com, kernel-team@meta.com, leitao@debian.org, leo.bras@arm.com, leo.yan@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, palmer@dabbelt.com, paulmck@kernel.org, puranjay@kernel.org, rmikey@meta.com, usama.arif@linux.dev, will@kernel.org Subject: [PATCH] arm64/daifflags: Make local_daif_*() helpers __always_inline Date: Mon, 27 Apr 2026 15:01:26 +0100 Message-ID: <20260427140125.1773574-2-leo.bras@arm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Make sure those helpers are always inlined and instrumentation safe. Signed-off-by: Leonardo Bras --- arch/arm64/include/asm/daifflags.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/daifflags.h b/arch/arm64/include/asm/daifflags.h index 5fca48009043..795b35128467 100644 --- a/arch/arm64/include/asm/daifflags.h +++ b/arch/arm64/include/asm/daifflags.h @@ -12,66 +12,66 @@ #include #include #define DAIF_PROCCTX 0 #define DAIF_PROCCTX_NOIRQ (PSR_I_BIT | PSR_F_BIT) #define DAIF_ERRCTX (PSR_A_BIT | PSR_I_BIT | PSR_F_BIT) #define DAIF_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT) /* mask/save/unmask/restore all exceptions, including interrupts. */ -static inline void local_daif_mask(void) +static __always_inline void local_daif_mask(void) { WARN_ON(system_has_prio_mask_debugging() && (read_sysreg_s(SYS_ICC_PMR_EL1) == (GIC_PRIO_IRQOFF | GIC_PRIO_PSR_I_SET))); asm volatile( "msr daifset, #0xf // local_daif_mask\n" : : : "memory"); /* Don't really care for a dsb here, we don't intend to enable IRQs */ if (system_uses_irq_prio_masking()) gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET); trace_hardirqs_off(); } -static inline unsigned long local_daif_save_flags(void) +static __always_inline unsigned long local_daif_save_flags(void) { unsigned long flags; flags = read_sysreg(daif); if (system_uses_irq_prio_masking()) { /* If IRQs are masked with PMR, reflect it in the flags */ if (read_sysreg_s(SYS_ICC_PMR_EL1) != GIC_PRIO_IRQON) flags |= PSR_I_BIT | PSR_F_BIT; } return flags; } -static inline unsigned long local_daif_save(void) +static __always_inline unsigned long local_daif_save(void) { unsigned long flags; flags = local_daif_save_flags(); local_daif_mask(); return flags; } -static inline void local_daif_restore(unsigned long flags) +static __always_inline void local_daif_restore(unsigned long flags) { bool irq_disabled = flags & PSR_I_BIT; WARN_ON(system_has_prio_mask_debugging() && (read_sysreg(daif) & (PSR_I_BIT | PSR_F_BIT)) != (PSR_I_BIT | PSR_F_BIT)); if (!irq_disabled) { trace_hardirqs_on(); if (system_uses_irq_prio_masking()) { @@ -117,21 +117,21 @@ static inline void local_daif_restore(unsigned long flags) write_sysreg(flags, daif); if (irq_disabled) trace_hardirqs_off(); } /* * Called by synchronous exception handlers to restore the DAIF bits that were * modified by taking an exception. */ -static inline void local_daif_inherit(struct pt_regs *regs) +static __always_inline void local_daif_inherit(struct pt_regs *regs) { unsigned long flags = regs->pstate & DAIF_MASK; if (!regs_irqs_disabled(regs)) trace_hardirqs_on(); if (system_uses_irq_prio_masking()) gic_write_pmr(regs->pmr); /* -- 2.54.0