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Peter Anvin" , Ajay Kaher , Alexey Makhalov , Broadcom internal kernel review list Subject: [PATCH RFC 09/11] x86/msr: Add macros for preparing to switch rdmsr/wrmsr interfaces Date: Tue, 28 Apr 2026 12:42:03 +0200 Message-ID: <20260428104205.916924-10-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260428104205.916924-1-jgross@suse.com> References: <20260428104205.916924-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-3.01 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; R_DKIM_ALLOW(-0.20)[suse.com:s=susede1]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MX_GOOD(-0.01)[]; RCPT_COUNT_TWELVE(0.00)[12]; RCVD_VIA_SMTP_AUTH(0.00)[]; MIME_TRACE(0.00)[0:+]; ARC_NA(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; TO_DN_SOME(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:106:10:150:64:167:received]; FROM_HAS_DN(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:dkim,suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo,imap1.dmz-prg2.suse.org:rdns]; RCVD_TLS_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; DNSWL_BLOCKED(0.00)[2a07:de40:b281:106:10:150:64:167:received,2a07:de40:b281:104:10:150:64:97:from]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; R_RATELIMIT(0.00)[to_ip_from(RLkdkdrsxe9hqhhs5ask8616i6)]; DKIM_TRACE(0.00)[suse.com:+] X-Rspamd-Queue-Id: DBBC26A844 X-Spam-Flag: NO X-Spam-Score: -3.01 X-Spam-Level: In order to prepare switching the rdmsr(), rdmasr_safe(), wrmsr() and wrmsr_safe() interfaces to 64-bit values instead of 32-bit pairs, add macros to call different implementations depending on the number of passed parameters. This enables to use the same function/macro names as today while doing the interface switch per component instead of one go. At the same time switch the rdmsr related interfaces to inline functions, avoiding to change variables passed as a parameter to be changed. The helper macros will be removed when all users of the current interfaces have been switched to the new ones. Signed-off-by: Juergen Gross --- arch/x86/include/asm/msr.h | 46 +++++++++++++++++++++++++++++---- arch/x86/include/asm/paravirt.h | 6 ++--- 2 files changed, 44 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index a5596d268053..4dd181aedb00 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -12,6 +12,7 @@ #include #include +#include #include #include @@ -179,14 +180,14 @@ static inline u64 native_read_pmc(int counter) * pointer indirection), this allows gcc to optimize better */ -#define rdmsr(msr, low, high) \ +#define __rdmsr_3(msr, low, high) \ do { \ u64 __val = native_read_msr((msr)); \ (void)((low) = (u32)__val); \ (void)((high) = (u32)(__val >> 32)); \ } while (0) -static inline void wrmsr(u32 msr, u32 low, u32 high) +static inline void __wrmsr_3(u32 msr, u32 low, u32 high) { native_write_msr(msr, (u64)high << 32 | low); } @@ -206,7 +207,7 @@ static inline int wrmsrq_safe(u32 msr, u64 val) } /* rdmsr with exception handling */ -#define rdmsr_safe(msr, low, high) \ +#define __rdmsr_safe_3(msr, low, high) \ ({ \ u64 __val; \ int __err = native_read_msr_safe((msr), &__val); \ @@ -243,13 +244,48 @@ static __always_inline void wrmsrns(u32 msr, u64 val) } /* - * Dual u32 version of wrmsrq_safe(): + * Dual u32 versions of wrmsr_safe(): */ -static inline int wrmsr_safe(u32 msr, u32 low, u32 high) +static __always_inline int __wrmsr_safe_3(u32 msr, u32 low, u32 high) { return wrmsrq_safe(msr, (u64)high << 32 | low); } +/* + * u64 versions of rdmsr/wrmsr[_safe](): + */ +static __always_inline u64 __rdmsr_1(u32 msr) +{ + u64 val; + + rdmsrq(msr, val); + + return val; +} + +static __always_inline void __wrmsr_2(u32 msr, u64 val) +{ + wrmsrq(msr, val); +} + +static __always_inline int __rdmsr_safe_2(u32 msr, u64 *p) +{ + return rdmsrq_safe(msr, p); +} + +static __always_inline int __wrmsr_safe_2(u32 msr, u64 val) +{ + return wrmsrq_safe(msr, val); +} + +/* + * Macros for selecting u64 or dual u32 versions of rdmsr/wrmsr[_safe](): + */ +#define rdmsr(...) CONCATENATE(__rdmsr_, COUNT_ARGS(__VA_ARGS__))(__VA_ARGS__) +#define wrmsr(...) CONCATENATE(__wrmsr_, COUNT_ARGS(__VA_ARGS__))(__VA_ARGS__) +#define rdmsr_safe(...) CONCATENATE(__rdmsr_safe_, COUNT_ARGS(__VA_ARGS__))(__VA_ARGS__) +#define wrmsr_safe(...) CONCATENATE(__wrmsr_safe_, COUNT_ARGS(__VA_ARGS__))(__VA_ARGS__) + struct msr __percpu *msrs_alloc(void); void msrs_free(struct msr __percpu *msrs); int msr_set_bit(u32 msr, u8 bit); diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h index cdfe4007443e..359fbc09f132 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -150,14 +150,14 @@ static inline int paravirt_write_msr_safe(u32 msr, u64 val) return PVOP_CALL2(int, pv_ops, cpu.write_msr_safe, msr, val); } -#define rdmsr(msr, val1, val2) \ +#define __rdmsr_3(msr, val1, val2) \ do { \ u64 _l = paravirt_read_msr(msr); \ val1 = (u32)_l; \ val2 = _l >> 32; \ } while (0) -static __always_inline void wrmsr(u32 msr, u32 low, u32 high) +static __always_inline void __wrmsr_3(u32 msr, u32 low, u32 high) { paravirt_write_msr(msr, (u64)high << 32 | low); } @@ -178,7 +178,7 @@ static inline int wrmsrq_safe(u32 msr, u64 val) } /* rdmsr with exception handling */ -#define rdmsr_safe(msr, a, b) \ +#define __rdmsr_safe_3(msr, a, b) \ ({ \ u64 _l; \ int _err = paravirt_read_msr_safe((msr), &_l); \ -- 2.53.0