From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out30-131.freemail.mail.aliyun.com (out30-131.freemail.mail.aliyun.com [115.124.30.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46DF0478E56; Tue, 28 Apr 2026 13:14:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777382082; cv=none; b=udbDO+A2/NhIi543qbIyXk0bJfbRfO5CtgYvifJfdSI826G8IxKaHTQuBCEVOhhDNGRPt/kWZxRFR2FjFoWcn/d5fiqSM3GZgWvzxSK5FlRzik058mP1rpyasYTDJwhSrQDYSRvq8Gm1wZzdqwQp2rlJiZwEdGoauDLEyQRMyKo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777382082; c=relaxed/simple; bh=qEbL7NazfstBPbALI9WwA7iUCsNKl7ldy/g2UhgQkbQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Z0PLojV1ZzGcDGhDx9Q25VUxmCjnsa98TB7Amz2F/mmSoZtXxYfv6iQ49sc7JPIAFDw3iw+1t4UrgIM8H+ewQ0g38MPb8/rmmyK5NZytA/m1/JtdeP5Oq+Da5ToFP+dXezrQLhnHJlStF17zwPZAatbOo5deW1BDLqFmGyOOf24= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=H8PpUuUD; arc=none smtp.client-ip=115.124.30.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="H8PpUuUD" DKIM-Signature:v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1777382077; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=GTaXyo6u6wVsR7hfJRYDUBPmXTghSbJ0+BI4PVwt11c=; b=H8PpUuUDWrG2qxO4FDj3a0AJZ+pEyFbh8hPyeFL4A1qhuVBg4gykoZvlpGnODtD+F+hi8sE1m0DBiKCSwIf2WmTYm1957gex4h2dUTvx+0BvYYaHxLGdEAhFehrMN+wbtDSCma5EUw0EMRSFUP44oh3HcoTQUYbo4GVcm/7WAdU= X-Alimail-AntiSpam:AC=PASS;BC=-1|-1;BR=01201311R191e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033037033178;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=24;SR=0;TI=SMTPD_---0X1ubIIu_1777382072; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0X1ubIIu_1777382072 cluster:ay36) by smtp.aliyun-inc.com; Tue, 28 Apr 2026 21:14:33 +0800 From: fangyu.yu@linux.alibaba.com To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com, baolu.lu@linux.intel.com, vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com, jgg@nvidia.com Cc: guoren@kernel.org, kvm@vger.kernel.org, iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Zong Li , Fangyu Yu Subject: [RFC PATCH 11/11] iommu/riscv: support nested iommu for getting iommu hardware information Date: Tue, 28 Apr 2026 21:13:59 +0800 Message-Id: <20260428131359.34872-12-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260428131359.34872-1-fangyu.yu@linux.alibaba.com> References: <20260428131359.34872-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Zong Li This patch implements .hw_info operation and the related data structures for passing the IOMMU hardware capabilities for iommufd. Signed-off-by: Zong Li Reviewed-by: Jason Gunthorpe Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 19 +++++++++++++++++++ include/uapi/linux/iommufd.h | 18 ++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index cb9d315e82ee..9abf446e1b85 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1556,8 +1556,27 @@ static void riscv_iommu_release_device(struct device *dev) kfree_rcu_mightsleep(info); } +static void *riscv_iommu_hw_info(struct device *dev, u32 *length, u32 *type) +{ + struct riscv_iommu_device *iommu = dev_to_iommu(dev); + struct iommu_hw_info_riscv_iommu *info; + + info = kzalloc_obj(*info); + if (!info) + return ERR_PTR(-ENOMEM); + + info->capability = iommu->caps; + info->fctl = riscv_iommu_readl(iommu, RISCV_IOMMU_REG_FCTL); + + *length = sizeof(*info); + *type = IOMMU_HW_INFO_TYPE_RISCV_IOMMU; + + return info; +} + static const struct iommu_ops riscv_iommu_ops = { .of_xlate = riscv_iommu_of_xlate, + .hw_info = riscv_iommu_hw_info, .capable = riscv_iommu_capable, .identity_domain = &riscv_iommu_identity_domain, .blocked_domain = &riscv_iommu_blocking_domain, diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index e998dfbd6960..79d3dc5e8d19 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -660,6 +660,22 @@ struct iommu_hw_info_amd { __aligned_u64 efr2; }; +/** + * struct iommu_hw_info_riscv_iommu - RISCV IOMMU hardware information + * + * @capability: Value of RISC-V IOMMU capability register defined in + * RISC-V IOMMU spec section 5.3 IOMMU capabilities + * @fctl: Value of RISC-V IOMMU feature control register defined in + * RISC-V IOMMU spec section 5.4 Features-control register + * + * Don't advertise ATS support to the guest because driver doesn't support it. + */ +struct iommu_hw_info_riscv_iommu { + __aligned_u64 capability; + __u32 fctl; + __u32 __reserved; +}; + /** * enum iommu_hw_info_type - IOMMU Hardware Info Types * @IOMMU_HW_INFO_TYPE_NONE: Output by the drivers that do not report hardware @@ -670,6 +686,7 @@ struct iommu_hw_info_amd { * @IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for ARM * SMMUv3) info type * @IOMMU_HW_INFO_TYPE_AMD: AMD IOMMU info type + * @IOMMU_HW_INFO_TYPE_RISCV_IOMMU: RISC-V iommu info type */ enum iommu_hw_info_type { IOMMU_HW_INFO_TYPE_NONE = 0, @@ -678,6 +695,7 @@ enum iommu_hw_info_type { IOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2, IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3, IOMMU_HW_INFO_TYPE_AMD = 4, + IOMMU_HW_INFO_TYPE_RISCV_IOMMU = 5, }; /** -- 2.50.1