From: Jason Gunthorpe <jgg@ziepe.ca>
To: fangyu.yu@linux.alibaba.com
Cc: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
alex@ghiti.fr, tjeznach@rivosinc.com, kevin.tian@intel.com,
baolu.lu@linux.intel.com, vasant.hegde@amd.com,
anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com,
guoren@kernel.org, kvm@vger.kernel.org, iommu@lists.linux.dev,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH 06/11] iommu/riscv: Add domain_alloc_paging_flags for second-stage domain
Date: Tue, 28 Apr 2026 10:35:01 -0300 [thread overview]
Message-ID: <20260428133501.GE849557@ziepe.ca> (raw)
In-Reply-To: <20260428131359.34872-7-fangyu.yu@linux.alibaba.com>
On Tue, Apr 28, 2026 at 09:13:54PM +0800, fangyu.yu@linux.alibaba.com wrote:
> From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
>
> Replace .domain_alloc_paging with .domain_alloc_paging_flags so callers
> can pass allocation flags to select the appropriate page-table type.
>
> When IOMMU_HWPT_ALLOC_NEST_PARENT or IOMMU_HWPT_ALLOC_DIRTY_TRACKING is
> set in @flags, allocate a second-stage (iohgatp) domain.
>
> When @flags is 0 the behaviour is identical to the previous
> domain_alloc_paging: first-stage (iosatp) domain.
>
> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
> ---
> drivers/iommu/riscv/iommu.c | 66 ++++++++++++++++++++++++++++---------
> 1 file changed, 51 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
> index 5dadf6d09139..0c13430ecc7f 100644
> --- a/drivers/iommu/riscv/iommu.c
> +++ b/drivers/iommu/riscv/iommu.c
> @@ -1255,23 +1255,50 @@ static const struct iommu_domain_ops riscv_iommu_paging_domain_ops = {
> .flush_iotlb_all = riscv_iommu_iotlb_flush_all,
> };
>
> -static struct iommu_domain *riscv_iommu_alloc_paging_domain(struct device *dev)
> +static struct iommu_domain *riscv_iommu_domain_alloc_paging_flags(
> + struct device *dev, u32 flags,
> + const struct iommu_user_data *user_data)
> {
> + const bool second_stage = flags &
> + (IOMMU_HWPT_ALLOC_NEST_PARENT | IOMMU_HWPT_ALLOC_DIRTY_TRACKING);
This isn't the right logic, you should follow the switch/case design
from other drivers.
> struct pt_iommu_riscv_64_cfg cfg = {};
> struct riscv_iommu_domain *domain;
> struct riscv_iommu_device *iommu;
> int ret;
>
> + if (user_data)
> + return ERR_PTR(-EOPNOTSUPP);
> +
> iommu = dev_to_iommu(dev);
> - if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV57) {
> - cfg.common.hw_max_vasz_lg2 = 57;
> - } else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV48) {
> - cfg.common.hw_max_vasz_lg2 = 48;
> - } else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV39) {
> - cfg.common.hw_max_vasz_lg2 = 39;
> +
> + if (second_stage) {
> + /*
> + * Second-stage (iohgatp) page table for KVM VFIO device
> + * pass-through and dirty tracking. The GPA space is 2 bits
> + * wider than the corresponding first-stage VA space (x4 root
> + * page table), so hw_max_vasz_lg2 values are 41/50/59.
> + */
> + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV57X4) {
> + cfg.common.hw_max_vasz_lg2 = 59;
> + } else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV48X4) {
> + cfg.common.hw_max_vasz_lg2 = 50;
> + } else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV39X4) {
> + cfg.common.hw_max_vasz_lg2 = 41;
> + } else {
> + dev_err(dev, "cannot find supported second-stage page table mode\n");
> + return ERR_PTR(-ENODEV);
Do not make log messages for failing system calls.
Jason
next prev parent reply other threads:[~2026-04-28 13:35 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-28 13:13 [RFC PATCH 00/11] iommu/riscv: Add hardware dirty tracking for second-stage domains fangyu.yu
2026-04-28 13:13 ` [RFC PATCH 01/11] iommupt: Add RISC-V Second-stage (iohgatp) page table support fangyu.yu
2026-04-28 13:32 ` Jason Gunthorpe
2026-04-29 1:06 ` fangyu.yu
2026-04-29 12:18 ` Jason Gunthorpe
2026-04-29 15:42 ` fangyu.yu
2026-04-28 13:13 ` [RFC PATCH 02/11] iommu/riscv: report iommu capabilities fangyu.yu
2026-04-28 13:33 ` Jason Gunthorpe
2026-04-29 1:15 ` fangyu.yu
2026-04-28 13:13 ` [RFC PATCH 03/11] iommu/riscv: use data structure instead of individual values fangyu.yu
2026-04-28 13:13 ` [RFC PATCH 04/11] iommu/riscv: support GSCID and GVMA invalidation command fangyu.yu
2026-04-28 13:13 ` [RFC PATCH 05/11] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch fangyu.yu
2026-04-28 13:13 ` [RFC PATCH 06/11] iommu/riscv: Add domain_alloc_paging_flags for second-stage domain fangyu.yu
2026-04-28 13:35 ` Jason Gunthorpe [this message]
2026-04-29 1:21 ` fangyu.yu
2026-04-28 13:13 ` [RFC PATCH 07/11] iommupt: Don't preset D when RISC-V IOMMU dirty tracking on fangyu.yu
2026-04-28 13:36 ` Jason Gunthorpe
2026-04-29 1:41 ` fangyu.yu
2026-04-28 13:13 ` [RFC PATCH 08/11] iommu/riscv: Add dirty tracking support for second-stage domains fangyu.yu
2026-04-28 13:38 ` Jason Gunthorpe
2026-04-29 1:46 ` fangyu.yu
2026-04-28 13:13 ` [RFC PATCH 09/11] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries fangyu.yu
2026-04-28 13:13 ` [RFC PATCH 10/11] iommupt: Add RISC-V dirty tracking PTE ops fangyu.yu
2026-04-28 13:39 ` Jason Gunthorpe
2026-04-29 1:52 ` fangyu.yu
2026-04-28 13:13 ` [RFC PATCH 11/11] iommu/riscv: support nested iommu for getting iommu hardware information fangyu.yu
2026-04-28 13:39 ` Jason Gunthorpe
2026-04-29 2:37 ` fangyu.yu
2026-05-04 19:53 ` [RFC PATCH 00/11] iommu/riscv: Add hardware dirty tracking for second-stage domains Andrew Jones
2026-05-05 13:48 ` fangyu.yu
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